US5101484A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and apparatus for implementing an iterative program loop by comparing the loop decrement with the loop value
Assignee: Intel Corp
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Filing: 1989-02-14
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Granted: 1992-03-31
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Expires: 2009-02-14
Abstract
Abstract A method and apparatus for providing program loop control in a data processor employs a special purpose instruction that substantially reduces the program overhead associated with conditional branching at the end of a program loop. The instruction first compares a loop counter with a decrement value. If the loop counter has counted down, a loop condition code, which is stored in a dedicated register bit, is cleared. Otherwise, the loop condition code remains set to indicate that further iterations of the loop are required. The decremented value of the loop counter is then stored in a loop counter register. In parallel with decrementing of the loop counter, a conditional branch is executed based on the value of the loop condition code set in the immediately previous iteration of the loop. If the loop condition code is cleared, i.e. if the loop has been completed, program control proceeds to the instruction following the loop after execution of the next instruction in sequence. conversely, if the loop condition code is set, program control returns to the branch address, i.e. the beginning of the loop, after execution of the next instruction in sequence. All of the operations of the present invention are performed within a single instruction cycle.
Inventors
- 👤 Leslie D. Kohn
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:28
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3808; G06F9/381; G06F9/32; G06F9/322; G06F9/325
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
262 words
In a computational apparatus for performing operations in synchronism with a clock signal, a method for performing a sequence of operations comprising the steps of: (a) initializing a loop count decrement and a loop condition code; (b) performing an iteration of said sequence of operations; (c) comparing said loop count with an absolute value of said loop count decrement in an arithmetic logic unit and providing a comparison output from the arithmetic logic unit to a temporary condition code register; (d) setting a temporary loop condition code in the temporary loop condition code register if said loop count is not less than said loop count decrement and clearing said temporary loop condition code if said loop count is less than said loop count decrement; (e) decreasing said loop count by said count decrement; (f) designating as a branch address a first of said sequence of operations if said loop condition code is set and designating as a branch address an operation sequentially following said sequence of operations if said loop condition code is cleared; and (g) setting said loop condition code equal to said temporary loop condition code; wherein steps (c), (d), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; whereby conditional branching is performed based on an initialized value of said loop count for a first iteration of said sequence of operations and is performed based on the value of said loop count in an immediately previous iteration of said sequence of operations in a second and subsequent iterations of said sequence of operations.
Claim 2
Dependent Claim
262 words
In a computational apparatus for performing operations in synchronism with a clock signal, a method for performing a sequence of operations comprising the steps of: (a) initializing a loop count decrement and a loop condition code; (b) performing an iteration of said sequence of operations; (c) comparing said loop count with an absolute value of said loop count decrement in an arithmetic logic unit and providing a comparison output from the arithmetic logic unit to a temporary condition code register; (d) setting a temporary loop condition code in the temporary loop condition code register if said loop count is not less than said loop count decrement and clearing said temporary loop condition code if said loop count is less than said loop count decrement; (e) decreasing said loop count by said count decrement; (f) designating as a branch address a first of said sequence of operations if said loop condition code is set and designating as a branch address an operation sequentially following said sequence of operations if said loop condition code is cleared; and (g) setting said loop condition code equal to said temporary loop condition code; wherein steps (c), (d), (e) and (f) are performed substantially concurrently during a single cycle of said clock signal; whereby conditional branching is performed based on an initialized value of said loop count for a first iteration of said sequence of operations and is performed based on the value of said loop count in an immediately previous iteration of said sequence of operations in a second and subsequent iterations of said sequence of operations.
Claim 3
Dependent Claim
16 words
The method of claim 1 wherein said loop condition code is stored in a dedicated location.
Claim 4
Dependent Claim
20 words
The method of claim 1 wherein said loop condition is stored in a dedicated bit of a processor status register.
Claim 5
Independent Claim
239 words
An apparatus for controlling iterative performance of a sequence of operations comprising: (a) first register means for storing a loop count; (b) second register means for storing a decrement value; (c) arithmetic logic means for receiving said loop count and said decrement value and for substantially concurrently decreasing said loop count by said decrement value, comparing said loop count with a two's complement of said decrement value, and providing a loop condition code indicating a result of said comparison; (d) third register means coupled to the arithmetic logic means for receiving and temporarily storing said loop condition code; (e) fourth register means coupled to said third register means for storing said loop condition code after a predetermined delay time; and (f) instruction fetch address means coupled to said fourth register means for designating a branch address based on said loop condition code, said branch address corresponding to a first of said sequence of operations if said loop condition code indicates said loop count is not less than said two's complement of said decrement value and said branch address corresponding to an operation sequentially following said sequence of operations if said loop condition code indicates said loop count is less than said two's complement of said decrement value; whereby said branch address which is determined substantially concurrently with said comparison performed by said arithmetic logic means is based on a loop condition code set prior to said predetermined delay time.
Claim 6
Independent Claim
239 words
An apparatus for controlling iterative performance of a sequence of operations comprising: (a) first register means for storing a loop count; (b) second register means for storing a decrement value; (c) arithmetic logic means for receiving said loop count and said decrement value and for substantially concurrently decreasing said loop count by said decrement value, comparing said loop count with a two's complement of said decrement value, and providing a loop condition code indicating a result of said comparison; (d) third register means coupled to the arithmetic logic means for receiving and temporarily storing said loop condition code; (e) fourth register means coupled to said third register means for storing said loop condition code after a predetermined delay time; and (f) instruction fetch address means coupled to said fourth register means for designating a branch address based on said loop condition code, said branch address corresponding to a first of said sequence of operations if said loop condition code indicates said loop count is not less than said two's complement of said decrement value and said branch address corresponding to an operation sequentially following said sequence of operations if said loop condition code indicates said loop count is less than said two's complement of said decrement value; whereby said branch address which is determined substantially concurrently with said comparison performed by said arithmetic logic means is based on a loop condition code set prior to said predetermined delay time.
Claim 7
Dependent Claim
19 words
The apparatus of claim 4 wherein said fourth register means comprises a dedicated bit of a processor status register.
Claim 8
Dependent Claim
18 words
The apparatus of claim 4 wherein said first and second register means are associated with a register file.
Claim 9
Dependent Claim
15 words
The apparatus fo claim 4 wherein said apparatus is included in a single chip microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-31 | 1995-09-30 | 1996-03-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-31 | 1999-09-30 | 2000-03-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-31 | 2003-09-30 | 2004-03-31 | $7700.00 | Window Closed / Lapsed |