Bus master for selectively disconnecting/connecting a first bus to and from a second bus in response to an acquisition request

Claim 1

A computer system comprising: a processor for executing processes constituting principal operations of said computer system; a first bus connected to said processor; a first bus master for executing predetermined processes; a second bus connected to said first bus master; bus connection and disconnection means for connecting and disconnecting said first bus to and from said second bus; and bus connection and disconnection control means connected to said bus connection and disconnection means for causing said bus connection and disconnection means to disconnect said first bus from said second bus when said first bus master requests acquisition of said second bus in parallel to a request from said processor such that said processor stays operational; wherein said bus connection and disconnection means includes: an address buffer for connecting an address bus of said first bus with an address bus of said second bus; a high-order data buffer for connecting a high-order byte data bus of said first bus with a high-order byte data bus of said second bus; a low-order byte data buffer for connecting a low-order byte data bus of said first bus with a low-order byte data bus of said second bus; a swap buffer for swapping data between the high-order byte data bus of said second bus and low-order byte data bus of said second bus; and buffer control means for converting a number of data bits between said first bus and said second bus through control over said address buffer, said high-order byte data buffer, said low-order byte data buffer and said swap buffer; and wherein when said processor or said first bus master makes an access to a device connected to said second bus, said bus connection and disconnection means sets in advance of the access a predetermined data width on a first data width identification signal regardless of an actual access data width of said device, and then said buffer control means is controlled based on the first data width identification signal and a second data width identification signal of said second bus such that data transfer is performed in a desired order even if a number of access bits of the device is different from said predetermined data width, said first data width identification signal indicating a number of bits which is recognized on the side of said first bus as a processing unit of bits, said second data width identification signal indicating a number of bits which the device processes at a time.