Microprocessor hold and lock circuitry

Claim 2

A hold and lock circuit, for use with a computer bus and a processor having an hold input port for receiving a hold signal, the processor being electrically coupled to the computer bus when the hold signal is in an inactive state, and decoupled from the bus when the hold signal is in an active state, said hold and lock circuit comprising in combination: a hold output port for sending a hold signal to said processor, said hold output port being connectable to said hold input port of said processor; a hold request input port for receiving a hold request signal; means for sending a hold request signal to said hold request input port; bus locking means, coupled between said hold output port and said hold request input port, for locking said hold signal in an inactive state in response to a change in said hold request signal from an active to an inactive state; and first bus unlocking means, coupled between said hold output port and said hold request input port, for unlocking said hold signal from the inactive state at a predetermined period of time after said hold request signal changes from the active to the inactive state, said predetermined period of time having a beginning and an end.

Claim 3

The hold and lock circuit of claim 1, including second bus unlocking means, coupled between said hold output port and said hold request input port, for unlocking said hold signal from the inactive state after a predetermined number of idle processor clock cycles following the change of said hold request signal from the active to the inactive state, said predetermined number of idle processor clock cycles having a beginning and an end.

Claim 4

The hold and lock circuit of claim 2, including means, coupled between said hold output port and said hold request input port, for generating a lockbus signal, said hold signal being held in the inactive state in response to an active lockbus signal, said lockbus signal being in an active state in response to an active hold request signal and an active hold signal, or an active lockbus signal and an inactive timer signal and an inactive idle signal during a previous clock cycle of the processor, wherein said timer signal is active at the end of said predetermined period of time, and said idle signal is active at the end of said predetermined number of idle processor clock cycles.

Claim 5

The hold and lock circuit of claim 3, including a timer circuit having an input for receiving said lockbus signal, said timer circuit being enabled when said lockbus signal is active, said timer circuit having an output for said timer signal.

Claim 6

The hold and lock circuit of claim 4, including means for generating a hold acknowledge signal, said hold acknowledge signal being active in response to active hold and hold request signals, said means for generating a hold acknowledge signal being coupled to said hold output port and said hold request input port.

Claim 7

The hold and lock circuit of claim 1, including means, coupled between said hold output port and said hold request input port, for generating a lockbus signal, said hold signal being held in the inactive state in response to an active lockbus signal, said lockbus signal being in an active state in response to an active hold request signal and an active hold signal, or an active lockbus signal and an inactive timer signal during a previous processor clock cycle, wherein said timer signal is active at the end of said predetermined period of time.

Claim 8

The hold and lock circuit of claim 6, including a timer circuit having an input for receiving said lockbus signal, said timer being enabled when said lockbus signal is active, said timer circuit having an output for said timer signal.

Claim 9

The hold and lock circuit of claim 7, including means, coupled between said hold output port and said hold request input port, for generating a hold acknowledge signal, said hold acknowledge signal being active in response to active hold and hold request signals.

Claim 10

A computer system comprising in combination: a computer bus; a processor having a hold input port, said processor being electrically coupled to said bus in response to a signal at said hold input port in an inactive state, and said processor being electrically decoupled from said bus in response to a signal at said hold input port in an active state; hold and lock circuitry having a hold request input port, said hold and lock circuitry sending a hold signal to said hold input port of said processor, said hold signal being locked in the inactive state in response to a change in the state of a signal at said hold request input port from an active to an inactive state, such that said processor is coupled to said bus when said hold signal is locked in the inactive state; said hold and lock circuitry including first means, coupled between said hold output port and said hold request input port, for unlocking said hold signal from the inactive state at a predetermined period of time after the signal at said hold request input port changes from the active to the inactive state, said predetermined period of time having a beginning and an end, said first means for unlocking said hold signal being coupled to said hold request input port; and means for sending a hold request signal to said hold request input port of said hold and lock circuitry.

Claim 11

A computer system comprising in combination: a computer bus; a processor having a hold input port, said processor being electrically coupled to said bus in response to a signal at said hold input port in an inactive state, and said processor being electrically decoupled from said bus in response to a signal at said hold input port in an active state; hold and lock circuitry having a hold request input port, said hold and lock circuitry sending a hold signal to said hold input port of said processor, said hold signal being locked in the inactive state in response to a change in the state of a signal at said hold request input port from an active to an inactive state, such that said processor is coupled to said bus when said hold signal is locked in the inactive state; said hold and lock circuitry including first means, coupled between said hold output port and said hold request input port, for unlocking said hold signal from the inactive state at a predetermined period of time after the signal at said hold request input port changes from the active to the inactive state, said predetermined period of time having a beginning and an end, said first means for unlocking said hold signal being coupled to said hold request input port; and means for sending a hold request signal to said hold request input port of said hold and lock circuitry.

Claim 12

The computer system of claim 9, wherein said hold and lock circuitry includes second means, coupled between said hold output port and said hold request input port, for unlocking said hold signal from the inactive state after a predetermined number of idle processor clock cycles following the change of said hold request signal from the active to the inactive state, said predetermined number of processor clock cycles having a beginning and an end.

Claim 13

The computer system of claim 10, wherein said hold and lock circuitry includes means, coupled between said hold output port and said hold request input port, for generating a lockbus signal, said hold signal being held in the inactive state in response to an active lockbus signal, said lockbus signal being in an active state in response to an active hold request signal and an active hold signal, or an active lockbus signal and an inactive timer signal and an inactive idle signal during a previous clock cycle, wherein said timer signal is in an active state at the end of said predetermined period of time, and said idle signal is active at the end of said predetermined number of idle processor clock cycles.

Claim 14

The computer system of claim 11, wherein said hold and lock circuitry includes a timer circuit having an input for receiving said lockbus signal, said timer circuit being enabled when said lockbus signal is active, said timer circuit having an output for said timer signal.

Claim 15

The computer system of claim 12, wherein said hold and lock circuitry includes means, coupled between said hold output port and said hold request input port, for generating a hold acknowledge signal, said hold acknowledge signal being active in response to active hold and hold request signals.

Claim 16

The computer system of claim 9, wherein said hold and lock circuitry includes means, coupled between said hold output port and said hold request input port, for generating a lockbus signal, said hold signal being held in the inactive state in response to an active lockbus signal, said lockbus signal being in an active state in response to an active hold request signal and an active hold signal, or an active lockbus signal and an inactive timer signal during a previous clock cycle, wherein said timer signal is active at the end of said predetermined period of time.

Claim 17

The computer system of claim 14, wherein said hold and lock circuitry includes a timer circuit having an input for receiving said lockbus signal, said timer being enabled when said lockbus signal is active, said timer circuit having an output for said timer signal.

Claim 18

The computer system of claim 15, wherein said hold and lock circuitry includes means, coupled between said hold output port and said hold request input port, for generating a hold acknowledge signal, said hold acknowledge signal being active in response to active hold and hold request signals.