Patent US5504432A successfully refreshed from Google Patents.
US5504432A
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System and method for detecting short, opens and connected pins on a printed circuit board using automatic test equipment
Assignee: Agilent Technologies Inc
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Filing: 1993-08-31
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Granted: 1996-04-02
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Expires: 2013-08-31
Abstract
Abstract An automatic circuit board tester for testing for shorts, opens, and interconnected pins or nodes on a circuit board. The tester first classifies the nodes as being in one of three categories based upon the design of the board and the intended interconnection of the nodes. The categories of nodes are: (1) connected to ground; (2) interconnected to all other nodes in the test group; or (3) isolated from all other nodes. The circuit board tester has a testhead containing a plurality of test channels, each configured to be coupled to a node on the circuit board. The testhead utilizes a digital signal from a digital driver to drive the node at a predetermined voltage and a digital receiver to read the node voltage to determine if it is coupled to ground. Each test channel also includes a switch to connect the digital driver and receiver to the test node as well as a ground switch to selectively couple the node to ground. Various combinations of switch positions and testing sequences enables the circuit board tester to test all node connections and to ensure that the physical embodiment of the circuit board accurately reflects the circuit board design.
Inventors
- 👤 Kevin G. Chandler
- 👤 Barry A. Alcorn
- 👤 Bryan D. Boswell
- 👤 John M. Heumann
- 👤 Ed O. Schlotzhauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 15:38
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3183; G01R31/318342; G01R31/2801; G01R31/281; G01R31/2812; G01R31/319; G01R31/31903; G01R31/31915; G01R31/31908; G01R31/3191
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
340 words
A method for testing node interconnection on a circuit board having a plurality of nodes using an automated test system comprising a plurality of test channels, each of the plurality of test channels including a digital driver having a first input and a first output, a digital receiver having a second output and a second input coupled to the first output, a ground switch, coupled to the first output and the second input, configured to selectively couple the first output and the second input to ground, and a test probe, coupled to the first output and the second input, configured to couple the first output and second input to a node, the method comprising the steps of: (1) classifying each node of the plurality of nodes into one or more classes based upon an intended interconnection of each node, said one or more classes including, (a) a first class of nodes for which said intended interconnection is a connection to ground, (b) a second class of nodes for which said intended interconnection is a connection to at least one other of the plurality of nodes, and (c) a third class of nodes for which said intended interconnection is neither a connection to ground nor a connection to any other of the plurality of nodes; (2) selecting one of a plurality of test node groups, each of said test node groups being associated with one of said classes of nodes such that all nodes in each of said test node groups have the same intended interconnection; (3) performing a ground short test on all nodes in said selected test node group when said associated class of nodes is said first class of nodes; (4) performing a connection test on all pair combinations of said nodes in said selected test node group when said associated class of nodes is said second class of nodes; and (5) performing an isolation test on all said nodes in said selected test node group when said associated class of nodes is said third class of nodes.
Claim 2
Independent Claim
340 words
A method for testing node interconnection on a circuit board having a plurality of nodes using an automated test system comprising a plurality of test channels, each of the plurality of test channels including a digital driver having a first input and a first output, a digital receiver having a second output and a second input coupled to the first output, a ground switch, coupled to the first output and the second input, configured to selectively couple the first output and the second input to ground, and a test probe, coupled to the first output and the second input, configured to couple the first output and second input to a node, the method comprising the steps of: (1) classifying each node of the plurality of nodes into one or more classes based upon an intended interconnection of each node, said one or more classes including, (a) a first class of nodes for which said intended interconnection is a connection to ground, (b) a second class of nodes for which said intended interconnection is a connection to at least one other of the plurality of nodes, and (c) a third class of nodes for which said intended interconnection is neither a connection to ground nor a connection to any other of the plurality of nodes; (2) selecting one of a plurality of test node groups, each of said test node groups being associated with one of said classes of nodes such that all nodes in each of said test node groups have the same intended interconnection; (3) performing a ground short test on all nodes in said selected test node group when said associated class of nodes is said first class of nodes; (4) performing a connection test on all pair combinations of said nodes in said selected test node group when said associated class of nodes is said second class of nodes; and (5) performing an isolation test on all said nodes in said selected test node group when said associated class of nodes is said third class of nodes.
Claim 3
Dependent Claim
84 words
The method of claim 1, further comprising the steps of: (6) before said step (3), initializing each of the plurality of test channels, said initializing step comprising the steps of: (a) calibrating the digital driver to output a test signal having a voltage sufficiently low such that applying said test signal to the circuit board does not activate semiconductor junctions located on the circuit board; and (b) calibrating the digital receiver to indicate when a predetermined threshold voltage is presented at the second input.
Claim 4
Dependent Claim
99 words
The method of claim 1, wherein said ground short test of said step (3) comprises the steps of: (a) applying a test signal to a selected node of the plurality of nodes by the digital driver; (b) a predetermined amount of time after said application of said test signal, reading a node voltage of said selected node by the digital receiver; (c) comparing said node voltage to a predetermined threshold voltage by the digital receiver; and (d) indicating that said selected node is not coupled to ground based on said comparison of said node voltage to said threshold voltage.
Claim 5
Dependent Claim
23 words
The method of claim 3, wherein said predetermined amount of time is a function of an impedance-capacitance time constant of said selected node.
Claim 6
Dependent Claim
100 words
The method of claim 1, wherein said connection test of said step (4) comprising the steps of: (a) coupling a first selected node and a second selected node to a first and a second test channel, respectively, of the plurality of test channels; (b) determining if said first selected node is connected to ground; (c) connecting said second selected node to ground; (d) applying a test signal to said first selected node via the digital driver of said first testing channel; and (e) repeating step (b) to determine if said first selected node and said selected second node are connected.
Claim 7
Dependent Claim
214 words
The method of claim 1, wherein said isolation test of said step (5) comprises the steps of: (a) coupling each node of said selected test node group to one of said plurality of test channels; (b) applying a test signal to said first selected node via the digital driver of a first testing channel coupled to said first selected node while grounding all remaining nodes of said selected test node group; (c) determining if a first digital receiver of said first testing channel indicates that said first selected node is isolated from said all remaining nodes of said selected test node group; (d) repeating steps (b) and (c) while isolating said all remaining nodes of said selected test node group from ground when step (d) indicates that said first selected test node is not isolated, thereby determining if the node is directly connected to ground; (e) repeating steps (a) through (d) for said all of said nodes of said selected test node group when said step (d) indicates that said selected node is directly shorted to ground; and (f) repeating step (d) for progressively smaller groups of said all remaining nodes of said selected test node group until all of said nodes of said remaining nodes with which the node is connected are identified.
Claim 8
Dependent Claim
20 words
The method of claim 1, wherein said classification is obtained from a node classification library stored on a host computer.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-02 | 1999-10-02 | 2000-04-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-02 | 2003-10-02 | 2004-04-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-02 | 2007-10-02 | 2008-04-02 | $7700.00 | Window Closed / Lapsed |