Solid state peripheral storage device

Claim 1

A solid state peripheral storage device for interfacing with a computer providing a command signal, a first address signal and a data signal; said device comprising: first register means for storing said command signal and said first address signal; second register means for storing said data signal; first memory means for storing a table of conversion of said first address signal into a second address signal, said first memory means comprising a plurality of floating gate storage cells; a dual port memory means having two ports, a first port and a second port with said first port in communication with said second register means; second memory means for storing said data signal, said second memory means comprising a plurality of floating gate storage cells; and sequencer means for receiving said command signal and said first address signal, and connected to said first memory means for converting said first address signal into said second address signal; said sequencer having means for addressing said second memory means with said second address signal to store said data signals therein, or to retrieve stored data signals therefrom; said sequencer further having means for correcting said stored data signals and to provide said corrected stored data signals to said second port of said dual port memory means.