Defect tolerant self-testing self-repairing memory system

Claim 2

A defect-tolerant memory system, capable of performing after manufacture a plurality of periodic self-test self-repair operations on itself during continuous operational use, comprising: a plurality of memory chips having a plurality of memory cells including (1) replacement memory cells, and (2) an as yet uncharacterized mix of good memory cells and defective memory cells; first means for testing and as a result characterizing each of said plurality of memory cells as being one of a plurality of good memory cells and a plurality of defective memory cells; and second means: (i) coupled to communicate with said first means: (1) for causing the first means to periodically test and characterize some or all of said memory cells using test data in a manner other than the storage and retrieval of actual working data; and (2) to receive the characterizing result; (ii) coupled to communicate with said replacement memory cells; and (iii) capable of causing, as a result of said characterizing result, said memory system to either: (1) continue to use one or more defective memory cells; and (2) replace one or more defective memory cells with replacement memory cells.

Claim 3

A memory system as in claim 1, which includes only acceptable memory chips having passed a test for and thereby being known to be free of, gross defects.

Claim 4

A memory system as in claim 1 wherein said first means comprises an error correction code (ECC) engine.

Claim 5

A memory system as in claim 3 wherein said second means causes said first means to test and characterize said memory cells, using a test pattern, upon detecting an error during the storage and/or retrieval of actual working data which cannot be corrected by said error correction code engine.

Claim 6

A memory system as in claim 3 wherein said memory system continues to use one or more defective memory cells when errors caused by one or more defective memory cells can be corrected by said error correction code engine.

Claim 7

A memory system as in claim 3 wherein said memory system replaces one or more defective memory cells when errors caused by said one or more defective memory cells cannot be corrected by said error correction code engine.

Claim 8

A memory system as in claim 1 wherein said second means comprises a system controller.

Claim 9

A memory system as in claim 1, further comprising a substitute address table accessible by said second means to retrievably store an address of a defective memory cell and a related address of a replacement memory cell.

Claim 10

A memory system as in claim 1 wherein said second means causes said first means to test and characterize said memory cells, using a test pattern, upon application of power to said memory system.

Claim 11

A memory system as in claim 1 wherein said second means causes said first means to test and characterize said memory cells, using a test pattern, upon detecting an error during the storage and/or retrieval of actual working data.

Claim 12

A defect tolerant memory system, capable of performing after manufacture a plurality of periodic self-test self-repair operations on itself during continuous operational use, comprising: a plurality of individual integrated circuit memory chips each comprising a plurality of individual memory cells, said plurality of memory chips including replacement memory cells and an as yet uncharacterized mix of: (1) good memory cells that function as intended; and (2) defective memory cells that do not function as intended; first means for testing and as a result characterizing each of said plurality of individual memory cells, including said replacement memory cells, as being one of a plurality of good memory cells and a plurality of defective memory cells; second means: coupled to said first means for causing the first means to periodically test and characterize the memory cells using test data in a manner other than the storage and retrieval of actual working data; coupled to the said first means to receive the result characterizing the memory cells as good memory cells and defective memory cells; and a substitute address table accessible by said second means, said substitute address table being capable of storing an address a replacement memory cell corresponding to a defective memory cell, said second means being capable of causing, as a result of a characterizing result, said memory system to either: (1) continue to use one or more of said defective memory cells; and (2) to store one or more addresses of replacement memory cells in said substitute address memory so as to replace one or more defective memory cells with said replacement memory cells.

Claim 13

A defect tolerant memory system, capable of performing after manufacture a plurality of periodic self-test self-repair operations on itself during continuous operational use, comprising: a plurality of individual integrated circuit memory chips each comprising a plurality of individual memory cells, said plurality of memory chips including replacement memory cells and an as yet uncharacterized mix of: (1) good memory cells that function as intended; and (2) defective memory cells that do not function as intended; first means for testing and as a result characterizing each of said plurality of individual memory cells, including said replacement memory cells, as being one of a plurality of good memory cells and a plurality of defective memory cells; second means: coupled to said first means for causing the first means to periodically test and characterize the memory cells using test data in a manner other than the storage and retrieval of actual working data; coupled to the said first means to receive the result characterizing the memory cells as good memory cells and defective memory cells; and a substitute address table accessible by said second means, said substitute address table being capable of storing an address a replacement memory cell corresponding to a defective memory cell, said second means being capable of causing, as a result of a characterizing result, said memory system to either: (1) continue to use one or more of said defective memory cells; and (2) to store one or more addresses of replacement memory cells in said substitute address memory so as to replace one or more defective memory cells with said replacement memory cells.

Claim 14

A memory system as in claim 11 wherein said second means causes said first means to test and characterize said memory cells, using a test pattern, upon application of power to said memory system.

Claim 15

A memory system as in claim 11 wherein said second means causes said first means to test and characterize said memory cells, using a test pattern, upon detecting an error during the storage and/or retrieval of actual working data.

Claim 16

A memory system as in claim 11 which includes only acceptable memory chips having passed a test for, and thereby being known to be free of, gross defects.

Claim 17

A memory system as in claim 11 wherein said first means comprises an error correction code (ECC) engine.

Claim 18

A memory system as in claim 15 wherein said second means causes said first means to test and characterize said memory cells, using a test pattern, upon detecting an error during the storage and/or retrieval of actual working data which cannot be corrected by said error correction code engine.

Claim 19

A memory system as in claim 15 wherein said memory system continues to use one or more defective memory cells when errors caused by said one or more defective memory cells can be corrected by said error correction code engine.

Claim 20

A memory system as in claim 15 wherein said memory system replaces one or more defective memory cells when errors caused by said one or more defective memory cells cannot be corrected by said error correction code engine.

Claim 21

A memory system as in claim 11 wherein said second means comprises a system controller.

Claim 24

A method as in claim 20 wherein said step of routinely and periodically testing comprises the step of causing said first means to test and characterize said memory cells, using a test pattern, upon application of power to said memory system.

Claim 25

A method as in claim 20 wherein said step of routinely and periodically testing comprises using a test pattern to detect errors during the storage and/or retrieval of said test pattern.

Claim 26

A method as in claim 20 wherein said step of routinely and periodically testing comprises the step of detecting errors with an error correction code (ECC) engine of the memory system during the storage and/or retrieval of actual working data.