Patent US5500392A successfully refreshed from Google Patents.
US5500392A
Expired / Lapsed
US
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Planar process using common alignment marks for well implants
Assignee: Texas Instruments Inc
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Filing: 1994-06-13
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Granted: 1996-03-19
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Expires: 2014-06-13
Abstract
Abstract A preferred embodiment of the present invention is a method of forming a device on a semiconductor substrate of a first conductivity type, the method comprising: forming a semiconducting layer on the substrate; etching alignment marks in the semiconducting layer (102); forming a first mask on the semiconducting layer to expose portions of the semiconducting layer; introducing dopants of a second conductivity type opposite the first conductivity type into the exposed portions of the semiconducting layer to form high-voltage tanks (104); removing the first mask; annealing the dopants introduced to form high-voltage tanks of a second conductivity type (105); forming a second mask on the semiconducting layer to expose second portions of the semiconducting layer; introducing dopants of a second conductivity type into the exposed second portions of the semiconducting layer to form low-voltage tanks (106); removing the second mask; forming a third mask on the semiconducting layer to expose third portions of the semiconducting layer; introducing dopants of a first conductivity type into the exposed third portions of the semiconducting layer to form high-voltage tanks (107); removing the third mask; forming a fourth mask on the semiconducting layer to expose fourth portions of the semiconducting layer; introducing dopants of a first conductivity type into the exposed fourth portions of the semiconducting layer to form low-voltage tanks (108); and annealing dopants introduced to form high-voltage and low-voltage tanks of the first and second conductivity types.
Inventors
- 👤 James Reynolds
- 👤 Michael C. Smayling
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 12:17
CPC Classifications
H; H10; H10B; H10B41/00; H10B41/40; H10B41/42; H10B41/49; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0156; H10D84/02; H10D84/03; H10D84/038; H10P; H10P30/00; H10P30/20; H10P30/22; H10W; H10W46/00; H10W46/501
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
224 words
A method of forming a device on a semiconductor substrate of a first conductivity type, said method comprising the steps of: forming a semiconducting layer on said substrate; etching alignment marks in said semiconducting layer; forming a first mask on said semiconducting layer to expose portions of said semiconducting layer; introducing dopants of a second conductivity type opposite said first conductivity type into said exposed portions of said semiconducting layer to form high-voltage tanks; removing said first mask; annealing said dopants introduced to form high-voltage tanks of a second conductivity type; forming a second mask on said semiconducting layer to expose second portions of said semiconducting layer; introducing dopants of a second conductivity type into said exposed second portions of said semiconducting layer to form low-voltage tanks; removing said second mask; forming a third mask on said semiconducting layer to expose third portions of said semiconducting layer; introducing dopants of a first conductivity type into said exposed third portions of said semiconducting layer to form high-voltage tanks; removing said third mask; forming a fourth mask on said semiconducting layer to expose fourth portions of said semiconducting layer; introducing dopants of a first conductivity type into said exposed fourth portions of said semiconducting layer to form low-voltage tanks; and annealing dopants introduced to form high-voltage and low-voltage tanks of said first and second conductivity types.
Claim 2
Independent Claim
224 words
A method of forming a device on a semiconductor substrate of a first conductivity type, said method comprising the steps of: forming a semiconducting layer on said substrate; etching alignment marks in said semiconducting layer; forming a first mask on said semiconducting layer to expose portions of said semiconducting layer; introducing dopants of a second conductivity type opposite said first conductivity type into said exposed portions of said semiconducting layer to form high-voltage tanks; removing said first mask; annealing said dopants introduced to form high-voltage tanks of a second conductivity type; forming a second mask on said semiconducting layer to expose second portions of said semiconducting layer; introducing dopants of a second conductivity type into said exposed second portions of said semiconducting layer to form low-voltage tanks; removing said second mask; forming a third mask on said semiconducting layer to expose third portions of said semiconducting layer; introducing dopants of a first conductivity type into said exposed third portions of said semiconducting layer to form high-voltage tanks; removing said third mask; forming a fourth mask on said semiconducting layer to expose fourth portions of said semiconducting layer; introducing dopants of a first conductivity type into said exposed fourth portions of said semiconducting layer to form low-voltage tanks; and annealing dopants introduced to form high-voltage and low-voltage tanks of said first and second conductivity types.
Claim 3
Independent Claim
174 words
A method of simultaneously fabricating a memory cell and a drain extended field effect transistor in a semiconductor material of a first conductivity type, said method comprising: foxing alignment marks in said semiconductor material; forming a first tank region of a second conductivity type different from said first conductivity type in said semiconductor material; simultaneously forming a second tank region and a third tank region of said first conductivity type in said semiconductor material, said second tank region is located in said first tank region and said third tank region is spaced away from said first and second tank regions; simultaneously forming a first gate structure and a second gate structure insulatively disposed over said semiconductor material, said first gate structure overlies said first tank region and a portion of said second tank region and said second gate structure overlies said third tank region; and wherein said first tank region, said second tank region, said third tank region, said first gate structure and said second gate structure are positioned based on said alignment marks.
Claim 4
Independent Claim
174 words
A method of simultaneously fabricating a memory cell and a drain extended field effect transistor in a semiconductor material of a first conductivity type, said method comprising: foxing alignment marks in said semiconductor material; forming a first tank region of a second conductivity type different from said first conductivity type in said semiconductor material; simultaneously forming a second tank region and a third tank region of said first conductivity type in said semiconductor material, said second tank region is located in said first tank region and said third tank region is spaced away from said first and second tank regions; simultaneously forming a first gate structure and a second gate structure insulatively disposed over said semiconductor material, said first gate structure overlies said first tank region and a portion of said second tank region and said second gate structure overlies said third tank region; and wherein said first tank region, said second tank region, said third tank region, said first gate structure and said second gate structure are positioned based on said alignment marks.
Claim 5
Dependent Claim
56 words
The method of claim 2, wherein a third gate structure is simultaneously formed with said first and second gate structures and aligned using said alignment marks, a portion of said third gate structure is insulatively disposed over said third tank region and the remainder of said third gate structure is disposed over a field insulating region.
Claim 6
Dependent Claim
35 words
The method of claim 2 further comprising the step of fabricating a third gate structure which is insulatively disposed over said third tank region and situated between said semiconductor material and said second gate structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-03-19 | 1999-09-18 | 2000-03-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-03-19 | 2003-09-18 | 2004-03-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-03-19 | 2007-09-18 | 2008-03-19 | $7700.00 | Window Closed / Lapsed |