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US4981529A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor substrate provided with marks for alignment even under a resist film

Assignee: Mitsubishi Electric Corp
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Filing: 1989-08-28
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Granted: 1991-01-01
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Expires: 2009-08-28
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Abstract

Abstract A semiconductor substrate is provided with alignment marks for recognizing and deciding positions of registration of a wafer and a mask in a photolithographic step that is included in a process of manufacturing a semiconductor device. The alignment marks, X alignment marks and Y alignment marks in a preferred embodiment are arranged only on straight lines which are parallel to corresponding X and Y axes of a Cartesian Coordinate system for registration of the substrate the alignment marks which extend to avoid obstructions, such as steps defined along dicing lines that prevent flow of resist to be coated onto the semiconductor substrate.

Inventors

  • 👤 Kouichirou Tsujita

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 14:58
CPC Classifications
G; G03; G03F; G03F9/00; G03F9/70; G03F9/7073; G03F9/7076; H; H10; H10W; H10W46/00; H10W46/201; H10W46/501; H10W46/503; Y; Y10; Y10S; Y10S148/00; Y10S148/102

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 292 words
A semiconductor substrate, comprising: chips having sides selectively disposed on said surface of said substrate so as to prevent a flow, along dicing lines formed on the substrate, of a resist material to be coated on the substrate; and geometrically similar straight alignment marks provided on a surface of the substrate, for recognizing and deciding a position of registration of a wafer formed thereon and a mask used therewith in a photolithographic step included in the process of manufacturing a semiconductor device on the substrate, groups of said alignment marks being formed and distributed only along straight lines with the alignment marks in each group being evenly spaced apart, lengthwise mutually parallel, and aligned normal to a corresponding axis of a set of X-Y Cartesian coordinate axes, for determination of said positions of registration with respect to said corresponding axes being decided by said alignment marks, said alignment marks each extending so as to avoid said sides, wherein said chips are defined along dicing lines formed for dividing/separating the semiconductor substrate and are in the form of steps formed by selectively depositing a film on the semiconductor substrate, the dicing lines are provided along the respective directions of the coordinate axes, said alignment marks comprise a group of X alignment marks distributed only along the X-axis and each normal thereto for deciding X-coordinates of said positions of registration and a group of Y alignment marks distributed only along the Y-axis and each normal thereto for deciding Y-coordinates of said positions of registration, and said X alignment marks are arranged only between X dicing lines provided along the direction of the X-coordinate axis and said Y alignment marks are arranged only between Y dicing lines provided along the direction of the Y-coordinate axis.
Claim 2
Dependent Claim 292 words
A semiconductor substrate, comprising: chips having sides selectively disposed on said surface of said substrate so as to prevent a flow, along dicing lines formed on the substrate, of a resist material to be coated on the substrate; and geometrically similar straight alignment marks provided on a surface of the substrate, for recognizing and deciding a position of registration of a wafer formed thereon and a mask used therewith in a photolithographic step included in the process of manufacturing a semiconductor device on the substrate, groups of said alignment marks being formed and distributed only along straight lines with the alignment marks in each group being evenly spaced apart, lengthwise mutually parallel, and aligned normal to a corresponding axis of a set of X-Y Cartesian coordinate axes, for determination of said positions of registration with respect to said corresponding axes being decided by said alignment marks, said alignment marks each extending so as to avoid said sides, wherein said chips are defined along dicing lines formed for dividing/separating the semiconductor substrate and are in the form of steps formed by selectively depositing a film on the semiconductor substrate, the dicing lines are provided along the respective directions of the coordinate axes, said alignment marks comprise a group of X alignment marks distributed only along the X-axis and each normal thereto for deciding X-coordinates of said positions of registration and a group of Y alignment marks distributed only along the Y-axis and each normal thereto for deciding Y-coordinates of said positions of registration, and said X alignment marks are arranged only between X dicing lines provided along the direction of the X-coordinate axis and said Y alignment marks are arranged only between Y dicing lines provided along the direction of the Y-coordinate axis.
Claim 3
Dependent Claim 42 words
A semiconductor substrate provided with alignment marks in accordance with 1, wherein: said substrate is formed with a flat normal to said surface of said substrate, and one of said X and Y axes is oriented to be parallel to said flat.
Claim 4
Dependent Claim 42 words
A semiconductor substrate provided with alignment marks in accordance with 1, wherein: said substrate is formed with a flat normal to said surface of said substrate, and one of said X and Y axes is oriented to be parallel to said flat.

References Cited (Backward Citations)

US3928094A Cited
JPS60233823A Cited
JPS61168933A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1993-12-31 1994-07-02 1995-01-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1997-12-31 1998-07-02 1999-01-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2001-12-31 2002-07-02 2003-01-01 $7700.00 Window Closed / Lapsed

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