Method for fabricating a CCD image sensor with active transistor pixel

Claim 1

A method for fabricating an active transistor pixel charge coupled device comprising: forming a semiconductor substrate of a first conductivity type; forming a semiconductor layer of a second conductivity type in the substrate; forming virtual phase regions of the first conductivity type in the semiconductor layer, the virtual phase regions forming virtual phase potential wells for carriers of the second conductivity type; forming a transistor source region of a first conductivity type in the semiconductor layer and spaced apart from the virtual phase regions; forming an insulating layer on the semiconductor layer; forming a transistor gate electrode on the insulating layer and located above the semiconductor layer surrounding the transistor source region and between virtual phase regions, the transistor gate electrode forming a transistor potential well for carriers of the second conductivity type in response to a voltage; forming transfer gate electrodes above the insulating layer and separated from the transistor gate electrode by the virtual phase regions, the transfer gate electrodes forming transfer potential wells for carriers of the second conductivity type in response to a voltage.

Claim 2

A method for fabricating an active transistor pixel charge coupled device comprising: forming a semiconductor substrate of a first conductivity type; forming a semiconductor layer of a second conductivity type in the substrate; forming virtual phase regions of the first conductivity type in the semiconductor layer, the virtual phase regions forming virtual phase potential wells for carriers of the second conductivity type; forming a transistor source region of a first conductivity type in the semiconductor layer and spaced apart from the virtual phase regions; forming an insulating layer on the semiconductor layer; forming a transistor gate electrode on the insulating layer and located above the semiconductor layer surrounding the transistor source region and between virtual phase regions, the transistor gate electrode forming a transistor potential well for carriers of the second conductivity type in response to a voltage; forming transfer gate electrodes above the insulating layer and separated from the transistor gate electrode by the virtual phase regions, the transfer gate electrodes forming transfer potential wells for carriers of the second conductivity type in response to a voltage.