BICMOS cache TAG comparator having redundancy and separate read an compare paths

Claim 2

A cache TAG comparator, comprising: a TAG array of memory cells; a redundant array of memory cells for replacing defective memory cells of the TAG array; a plurality of data multiplexers, coupled to the TAG array and to the redundant array, a data multiplexer of the plurality of data multiplexers providing a TAG address bit having a logic state corresponding to the logic state of a selected one of the memory cells of either of the TAG array and the redundant array; a plurality of comparators, coupled to the plurality of data multiplexers, a comparator of the plurality of comparators coupled to a data multiplexer of the plurality of data multiplexers, the comparator receiving the TAG address bit and an input data bit, and providing a compare signal at an output terminal of a first logic state if the logic state of the TAG address bit is the same as a logic state of the input data bit, and providing the compare signal at a second logic state if the logic state of the TAG address bit is not the same as the logic state of the input data bit; and a BICMOS match logic circuit, coupled to the plurality of comparators, the BICMOS match logic circuit providing a match signal having the first logic state if all of the compare signals are a same logic state, and providing the match signal at the second logic state if all of the compare signals are not the same logic state.

Claim 3

The cache TAG comparator of claim 1, wherein the TAG array of memory cells comprises an array of static random access memory cells.

Claim 4

The cache TAG comparator of claim 1, wherein the BICMOS match logic circuit comprises a differential amplifier having first and second resistors and a plurality of bipolar transistors, a base of a bipolar transistor of the plurality of bipolar transistors coupled to the output terminal of the comparator of the plurality of comparators.

Claim 5

The cache TAG comparator of claim 3, further comprising: a sense amplifier having an input terminal coupled to the output terminal of the comparator of the plurality of comparators, and an output terminal; and an output buffer having an input terminal coupled to the output terminal of the sense amplifier, and an output terminal.

Claim 6

The cache TAG comparator of claim 1, wherein the data multiplexer comprises: a first P-channel transistor having a first source/drain terminal for receiving a first TAG address bit signal from a selected memory cell of the TAG array of memory cells, a gate for receiving a first control signal, and a second source/drain terminal; a second P-channel transistor having a first source/drain terminal coupled to the redundant array, a gate for receiving a second control signal, and a second source/drain terminal coupled to the second source/drain terminal of the first P-channel transistor; a third P-channel transistor having a first source/drain terminal for receiving a second TAG address bit signal from a selected memory cell of the TAG array of memory cells, the second TAG address bit signal being a logical complement of the first TAG address bit signal, a gate for receiving the first control signal, and a second source/drain terminal; and a fourth P-channel transistor having a first source/drain terminal coupled to the redundant array, a gate for receiving the second control signal, and a second source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor.

Claim 7

The cache TAG comparator of claim 5, wherein the comparator comprises: a fifth P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the first P-channel transistor, a gate for receiving a first input data bit signal, and a second source/drain terminal; a sixth P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the fifth P-channel transistor, a gate for receiving a second input data bit signal, the second input data bit signal being a logical complement of the first input data bit signal, and a second source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor; a seventh P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor, a gate coupled to the gate of the fifth P-channel transistor, and a second source/drain terminal; and an eighth P-channel transistor having a first source/drain terminal coupled to the first source/drain terminal of the fifth P-channel transistor, a gate coupled to the gate of the sixth P-channel transistor, and a second source/drain terminal coupled to the second source/drain terminal of the seventh P-channel transistor.

Claim 8

A cache TAG comparator, comprising: a TAG memory array for providing a predetermined number of TAG address bits in response to receiving an address; a plurality of local sense amplifiers, a local sense amplifier of the plurality of local sense amplifiers having an input terminal coupled to the TAG memory array for receiving one TAG address bit of the predetermined number of TAG address bits, and an output terminal; a plurality of comparators, a comparator of the plurality of comparators having a first input terminal coupled to the output terminal of the local sense amplifier, a second input terminal for receiving an input data bit of a plurality of input data bits, the comparator comparing a logic state of the one TAG address bit to a logic state of the input data bit, the comparator having an output terminal for providing a compare signal of a first logic state if the logic state of the one TAG address bit is the same as the logic state of the input data bit, and the comparator providing the compare signal at a second logic state if the logic state of the one TAG address bit is not the same as the logic state of the input data bit; and a BICMOS match logic circuit having a plurality of input terminals, each input terminal of the plurality of input terminals directly coupled to the output terminal of each comparator of the plurality of comparators, the BICMOS match logic circuit for comparing the compare signals of the plurality of comparators, and the BICMOS match logic circuit having an output terminal for providing a match signal if the compare signals from the plurality of comparators are the same logic state.

Claim 9

A cache TAG comparator, comprising: a TAG memory array for providing a predetermined number of TAG address bits in response to receiving an address; a plurality of local sense amplifiers, a local sense amplifier of the plurality of local sense amplifiers having an input terminal coupled to the TAG memory array for receiving one TAG address bit of the predetermined number of TAG address bits, and an output terminal; a plurality of comparators, a comparator of the plurality of comparators having a first input terminal coupled to the output terminal of the local sense amplifier, a second input terminal for receiving an input data bit of a plurality of input data bits, the comparator comparing a logic state of the one TAG address bit to a logic state of the input data bit, the comparator having an output terminal for providing a compare signal of a first logic state if the logic state of the one TAG address bit is the same as the logic state of the input data bit, and the comparator providing the compare signal at a second logic state if the logic state of the one TAG address bit is not the same as the logic state of the input data bit; and a BICMOS match logic circuit having a plurality of input terminals, each input terminal of the plurality of input terminals directly coupled to the output terminal of each comparator of the plurality of comparators, the BICMOS match logic circuit for comparing the compare signals of the plurality of comparators, and the BICMOS match logic circuit having an output terminal for providing a match signal if the compare signals from the plurality of comparators are the same logic state.

Claim 10

The cache TAG comparator of claim 7, wherein the TAG memory array is an array of static random access memory cells.

Claim 11

The cache TAG comparator of claim 7, further comprising a plurality of redundant columns of memory cells for replacing defective columns of the TAG memory array.

Claim 12

The cache TAG comparator of claim 9, wherein the one TAG address bit is characterized as being true and complement TAG address bit signals, and the input data bit is characterized as being true and complement input data bit signals.

Claim 13

The cache TAG comparator of claim 10, further comprising a data multiplexer, the data multiplexer comprising: a first P-channel transistor having a first source/drain terminal for receiving the true TAG address bit signal, a gate for receiving a first redundancy control signal, and a second source/drain terminal; a second P-channel transistor having a first source/drain terminal coupled to the plurality of redundant columns, a gate for receiving a second redundancy control signal, and a second source/drain terminal coupled to the second source/drain terminal of the first P-channel transistor; a third P-channel transistor having a first source/drain terminal for receiving the complement TAG address bit signal, a gate for receiving the first redundancy control signal, and a second source/drain terminal; and a fourth P-channel transistor having a first source/drain terminal coupled to the plurality of redundant columns, a gate for receiving the second redundancy control signal, and a second source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor.

Claim 14

The cache TAG comparator of claim 11, wherein the comparator comprises: a fifth P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the first P-channel transistor, a gate for receiving the complement input data bit signal, and a second source/drain terminal; a sixth P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the fifth P-channel transistor, a gate for receiving the true input data bit signal, and a second source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor; a seventh P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor, a gate coupled to the gate of the fifth P-channel transistor, and a second source/drain terminal; and an eighth P-channel transistor having a first source/drain terminal coupled to the first source/drain terminal of the fifth P-channel transistor, a gate coupled to the gate of the sixth P-channel transistor, and a second source/drain terminal coupled to the second source/drain terminal of the seventh P-channel transistor.

Claim 15

The cache TAG comparator of claim 12, further comprising a BICMOS driver circuit, the BICMOS driver circuit comprising: a first bipolar transistor having a collector coupled to a first power supply voltage terminal, a base coupled to the second source/drain terminal of the fifth P-channel transistor, and an emitter; a first N-channel transistor having a drain coupled to the emitter of the first bipolar transistor, a gate for receiving a compare mode control signal, and source; a second N-channel transistor having a drain coupled to the source of the first N-channel transistor, a gate for receiving a bias voltage, and a source coupled to a second power supply voltage terminal; and a third N-channel transistor having a drain coupled to the emitter of the bipolar transistor, a gate for receiving the bias voltage, and a source coupled to the second power supply voltage terminal.

Claim 16

The cache TAG comparator of claim 7, wherein the BICMOS match logic circuit comprises: a first resistor having a first terminal coupled to a first power supply voltage terminal, and a second terminal; a second resistor having a first terminal coupled the first power supply voltage terminal, and a second terminal; a plurality of first NPN transistors, each first NPN transistor of the plurality of first NPN transistors having a collector coupled to the second terminal of the first resistor, a base coupled to the output terminal of one of the plurality of comparators, and an emitter, each emitter of the plurality of first NPN transistors coupled together; a second NPN transistor having a collector coupled to the second terminal of the second resistor, a base for receiving a reference voltage, and an emitter coupled to the emitters of the plurality of first NPN transistors; a first N-channel transistor having a drain coupled to the emitters of the plurality of first NPN transistors, a gate for receiving a TAG select control signal, and a source; and a second N-channel transistor having a drain coupled the source of the first N-channel transistor, a gate for receiving a bias voltage, and a source coupled to a second power supply voltage terminal.

Claim 17

The cache TAG comparator of claim 14, wherein the BICMOS match logic circuit further comprises: an emitter-follower transistor having a collector coupled to the first power supply voltage terminal, a base coupled to the second terminal of the second resistor, and an emitter; a diode-connected transistor having a collector and a base coupled to the emitter of the emitter-follower transistor, and an emitter; a third N-channel transistor having a drain coupled to the emitter of the diode-connected transistor, a gate for receiving the TAG select control signal, and a source; and a fourth N-channel transistor having a drain coupled to the source of the third N-channel transistor, a gate for receiving the bias voltage, and a source coupled to the second power supply voltage terminal.

Claim 18

A cache TAG comparator, comprising: an array of memory cells arranged in intersecting rows and columns, the array for storing a TAG address of a predetermined number of bits, the array providing the TAG address of the predetermined number of bits in response to receiving an address; a plurality of redundant columns of memory cells, a redundant column of memory cells for replacing a defective column of the array; a plurality of local sense amplifiers of the predetermined number, a local sense amplifier of the plurality of local sense amplifiers having an input terminal coupled to the array of memory cells, and an output terminal for providing a TAG address bit signal corresponding to a TAG address bit of the predetermined number of bits; a redundant local sense amplifier having an input terminal coupled to the plurality of redundant columns of memory cells, and an output terminal for providing a redundant TAG address bit signal if a redundant column has replaced a defective column of the array; a plurality of data multiplexing and compare circuits of the predetermined number, a data multiplexing and compare circuit of the plurality of data multiplexing and compare circuits having a first input terminal for receiving the TAG address bit signal, a second input terminal coupled to the redundant local sense amplifier for receiving the redundant TAG address bit signal, a third input terminal for receiving an input data signal, the data multiplexing and compare circuit for comparing either the TAG address bit signal or the redundant TAG address bit signal to the input data signal in response to a redundant control signal, the data multiplexing and compare circuit having an output terminal for providing a compare signal of a first logic state if a logic state of the TAG address bit signal or the redundant TAG address bit signal is the same as a logic state of the input data signal, and the data multiplexing and compare circuit providing the compare signal at a second logic state if the logic state of the TAG address bit signal or the redundant TAG address bit signal is not the same as the logic state of the input data signal; and a BICMOS match logic circuit having a plurality of input terminals, each of the plurality of input terminals coupled to the output terminal of each of the plurality of data multiplexing and compare circuits, the BICMOS match logic circuit having an output terminal for providing a match signal if the compare signals of the plurality of data multiplexing and compare circuits are the same logic state.

Claim 19

A cache TAG comparator, comprising: an array of memory cells arranged in intersecting rows and columns, the array for storing a TAG address of a predetermined number of bits, the array providing the TAG address of the predetermined number of bits in response to receiving an address; a plurality of redundant columns of memory cells, a redundant column of memory cells for replacing a defective column of the array; a plurality of local sense amplifiers of the predetermined number, a local sense amplifier of the plurality of local sense amplifiers having an input terminal coupled to the array of memory cells, and an output terminal for providing a TAG address bit signal corresponding to a TAG address bit of the predetermined number of bits; a redundant local sense amplifier having an input terminal coupled to the plurality of redundant columns of memory cells, and an output terminal for providing a redundant TAG address bit signal if a redundant column has replaced a defective column of the array; a plurality of data multiplexing and compare circuits of the predetermined number, a data multiplexing and compare circuit of the plurality of data multiplexing and compare circuits having a first input terminal for receiving the TAG address bit signal, a second input terminal coupled to the redundant local sense amplifier for receiving the redundant TAG address bit signal, a third input terminal for receiving an input data signal, the data multiplexing and compare circuit for comparing either the TAG address bit signal or the redundant TAG address bit signal to the input data signal in response to a redundant control signal, the data multiplexing and compare circuit having an output terminal for providing a compare signal of a first logic state if a logic state of the TAG address bit signal or the redundant TAG address bit signal is the same as a logic state of the input data signal, and the data multiplexing and compare circuit providing the compare signal at a second logic state if the logic state of the TAG address bit signal or the redundant TAG address bit signal is not the same as the logic state of the input data signal; and a BICMOS match logic circuit having a plurality of input terminals, each of the plurality of input terminals coupled to the output terminal of each of the plurality of data multiplexing and compare circuits, the BICMOS match logic circuit having an output terminal for providing a match signal if the compare signals of the plurality of data multiplexing and compare circuits are the same logic state.

Claim 20

The cache TAG comparator of claim 16, wherein the TAG address bit signal is characterized as being first and second differential TAG address bit signals, the redundant TAG address bit signal is characterized as first and second differential redundant TAG address bit signals, and the input data signal being characterized as being first and second differential input data signals.

Claim 21

The cache TAG comparator of claim 17, wherein the data multiplexing and compare circuit comprises: a first P-channel transistor having a first source/drain terminal for receiving the first differential TAG address bit signal, a gate for receiving a first redundancy control signal, and a second source/drain terminal; a second P-channel transistor having a first source/drain terminal coupled to the plurality of redundant columns, a gate for receiving a second redundancy control signal, and a second source/drain terminal coupled to the second source/drain terminal of the first P-channel transistor; a third P-channel transistor having a first source/drain terminal for receiving the second differential TAG address bit signal, a gate for receiving the first redundancy control signal, and a second source/drain terminal; a fourth P-channel transistor having a first source/drain terminal coupled to the plurality of redundant columns, a gate for receiving the second redundancy control signal, and a second source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor; a fifth P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the first P-channel transistor, a gate for receiving the second input data signal, and a second source/drain terminal; a sixth P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the fifth P-channel transistor, a gate for receiving the first input data signal, and a second source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor; a seventh P-channel transistor having a first source/drain terminal coupled to the second source/drain terminal of the third P-channel transistor, a gate coupled to the gate of the fifth P-channel transistor, and a second source/drain terminal; and an eighth P-channel transistor having a first source/drain terminal coupled to the first source/drain terminal of the fifth P-channel transistor, a gate coupled to the gate of the sixth P-channel transistor, and a second source/drain terminal coupled to the second source/drain terminal of the seventh P-channel transistor.

Claim 22

The cache TAG comparator of claim 16, wherein the BICMOS match logic circuit comprises: a first resistor having a first terminal coupled to a first power supply voltage terminal, and a second terminal; a second resistor having a first terminal coupled to the first power supply voltage terminal, and a second terminal; a plurality of first NPN transistors, each first NPN transistor of the plurality of first NPN transistors having a collector coupled to the second terminal of the first resistor, a base coupled to the output terminal of one of the plurality of data multiplexing and compare circuits, and an emitter, each emitter of the plurality of first NPN transistors coupled together; a second NPN transistor having a collector coupled to the second terminal of the second resistor, a base for receiving a reference voltage, and an emitter coupled to the emitters of the plurality of first NPN transistors; a first N-channel transistor having a drain coupled to the emitters of the plurality of first NPN transistors, a gate for receiving a TAG select control signal, and a source; and a second N-channel transistor having a drain coupled to the source of the first N-channel transistor, a gate for receiving a bias voltage, and a source coupled to a second power supply voltage terminal.

Claim 23

The cache TAG comparator of claim 19, wherein the BICMOS match logic circuit further comprises: an emitter-follower transistor having a collector coupled to the first power supply voltage terminal, a base coupled to the second terminal of the second resistor, and an emitter; a diode-connected transistor having a collector and a base coupled to the emitter of the emitter-follower transistor, and an emitter; a third N-channel transistor having a drain coupled to the emitter of the diode-connected transistor, a gate for receiving the TAG select control signal, and a source; and a fourth N-channel transistor having a drain coupled to the source of the third N-channel transistor, a gate for receiving the bias voltage, and a source coupled to the second power supply voltage terminal.