Patent US5495570A successfully refreshed from Google Patents.
US5495570A
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Mirrored memory multi-processor system
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-10-26
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Granted: 1996-02-27
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Expires: 2014-10-26
Abstract
Abstract A multi-processor system having mirrored memory units accessible by either processor. The term "mirrored memory" in the context of the present invention describes the ability of each of the processors to directly READ and WRITE the contents of its own local random access memory (RAM) unit and in the local RAM unit of the other, remote processor. The mirrored memory of the present invention comprises two units of triple-ported RAM, each unit interconnected by a pair of interprocessor busses to the corresponding triple-ported RAM of the remote processor. "Triple-porting" describes the three input/output ports available for accessing a RAM unit. An internal port is used by a processor to access its local RAM, while the other two ports are provided so that the same RAM can be accessed by the remote processor through the paired interprocessor busses. Each processor may READ or WRITE its own local RAM, the remote processor's RAM, or both RAM's during a single operation. The present mirrored memory design facilitates concurrent and independent execution of both processors of a pair. Concurrent execution of both processors during mirrored RAM accesses is possible because the interprocessor busses are configurable as virtual dedicated ports (one for each processor). A method is also provided for equalizing the mirrored memory units of paired processors.
Inventors
- 👤 Randall W. Heugel
- 👤 Richard Mussett
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 17:05
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/16; G06F11/20; G06F11/2053; G06F11/2056; G06F11/2087; H; H04; H04L; H04L9/00; H04L9/40
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
183 words
A multiprocessor, shared memory system comprising at least two processors, each processor having: (a) at least two external communications paths; (b) a memory unit having at least three ports; (c) a processor and memory management unit coupled to the memory unit through a first port; (d) first coupling means for independently and directly coupling at least the other two ports of the memory unit to at least two of the external communications paths of another processor; (e) second coupling means independently and directly coupling the processor and memory management unit to at least two of the external communications paths of another processor; the first coupling means controlling data accesses to the memory unit by at least one other processor, and the second coupling means controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, whereby each processor is normally active and may, in a single operation, independently access only its memory, only the memory of at least one other processor, or both its memory and the memory of at least the other processor.
Claim 2
Dependent Claim
183 words
A multiprocessor, shared memory system comprising at least two processors, each processor having: (a) at least two external communications paths; (b) a memory unit having at least three ports; (c) a processor and memory management unit coupled to the memory unit through a first port; (d) first coupling means for independently and directly coupling at least the other two ports of the memory unit to at least two of the external communications paths of another processor; (e) second coupling means independently and directly coupling the processor and memory management unit to at least two of the external communications paths of another processor; the first coupling means controlling data accesses to the memory unit by at least one other processor, and the second coupling means controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, whereby each processor is normally active and may, in a single operation, independently access only its memory, only the memory of at least one other processor, or both its memory and the memory of at least the other processor.
Claim 3
Dependent Claim
79 words
The invention of claim 1, further including data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, and signaling an error condition if the accessed data values are not equivalent.
Claim 4
Dependent Claim
44 words
The invention of claim 2, wherein selected data generated by each processor and memory management unit of a processor is stored in a selected area of the memory unit of another processor, such that the selected data is mirrored in at least two processors.
Claim 5
Dependent Claim
54 words
The invention of claim 1, further including a duplex mode of operation, wherein the processor and memory management unit of a processor accesses the memory unit of another processor over a first external communications path, and the memory unit of the processor is accessed by the other processor over a second external communications path.
Claim 6
Dependent Claim
35 words
The invention of claim 4, wherein each of the processors can continue to access the memory unit of the other processor over one of the external communications paths if the other communications path is inoperative.
Claim 7
Dependent Claim
200 words
A multiprocessor, shared memory system comprising at least two processors, each processor having: (a) a memory unit having at least three ports; (b) a processor and memory management unit coupled to the memory unit through a first port; (c) at least first and second internal interprocessor interfaces, each coupled to the processor and memory management unit, and directly to respective second and third ports of the memory unit; (d) at least first and second external interprocessor interfaces, each coupled to a respective one of the at least first and second internal interprocessor interfaces, to the respective second and third ports of the memory unit, and to a corresponding external interprocessor interface of at least one other processor; the external and internal interprocessor interfaces controlling data accesses to the memory unit by at least one other processor, and controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, whereby each processor is normally active and may, in a single operation, independently access only its memory unit, only the memory unit of at least one other processor, or both its memory unit and the memory unit of at least one other processor.
Claim 8
Dependent Claim
200 words
A multiprocessor, shared memory system comprising at least two processors, each processor having: (a) a memory unit having at least three ports; (b) a processor and memory management unit coupled to the memory unit through a first port; (c) at least first and second internal interprocessor interfaces, each coupled to the processor and memory management unit, and directly to respective second and third ports of the memory unit; (d) at least first and second external interprocessor interfaces, each coupled to a respective one of the at least first and second internal interprocessor interfaces, to the respective second and third ports of the memory unit, and to a corresponding external interprocessor interface of at least one other processor; the external and internal interprocessor interfaces controlling data accesses to the memory unit by at least one other processor, and controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, whereby each processor is normally active and may, in a single operation, independently access only its memory unit, only the memory unit of at least one other processor, or both its memory unit and the memory unit of at least one other processor.
Claim 9
Dependent Claim
79 words
The invention of claim 6, further including data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, and signaling an error condition if the accessed data values are not equivalent.
Claim 10
Dependent Claim
44 words
The invention of claim 7, wherein selected data generated by each processor and memory management unit of a processor is stored in a selected area of the memory unit of another processor, such that the selected data is mirrored in at least two processors.
Claim 11
Dependent Claim
67 words
The invention of claim 6, further including a duplex mode of operation, wherein the processor and memory management unit of a processor accesses the memory unit of another processor through one coupled set of the first and second external interprocessor interfaces, and the memory unit of the processor is accessed by the other processor through the second coupled set of the first and second external interprocessor interfaces.
Claim 12
Dependent Claim
48 words
The invention of claim 9, wherein each of the processors can continue to access the memory unit of the other processor through one coupled set of the first and second external interprocessor interfaces if the other coupled set of the first and second external interprocessor interfaces is inoperative.
Claim 13
Dependent Claim
337 words
A multiprocessor, shared memory system comprising paired processors, each processor having: (a) a memory bus; (b) a memory unit coupled to the memory bus; (c) a processor bus; (d) a processor and memory management unit coupled to the processor bus; (e) a memory-processor interface coupled to the memory bus and the processor bus, for controlling transfers of data between the memory unit and the processor and memory management unit; (f) first and second external interprocessor interfaces each coupled to respective first and second internal interprocessor busses and to respective first and second external interprocessor busses, the first and second external interprocessor busses directly coupling each processor to the corresponding first and second external interprocessor busses of its paired processor, the first and second external interprocessor bus interfaces for controlling information transfers between the respective first and second external interprocessor busses and the respective first and second internal interprocessor busses; (g) first and second internal interprocessor interfaces, each respectively coupled to the first and second internal interprocessor busses and to the processor bus, for controlling information transfers between the respective first and second internal interprocessor busses and the processor bus; (h) first and second interprocessor-memory bus interfaces each respectively coupled to the first and second internal interprocessor busses and to the memory bus for controlling information transfers between the respective first and second internal interprocessor busses and the memory bus; and (i) data comparison means coupled to receive data from the memory unit of the processor and from the corresponding memory of its paired processor, for comparing the data accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of its paired processor, and signaling an error condition if the data accessed from the paired processors are not equivalent; whereby each processor is normally active and may, in a single operation, independently access only its memory unit, only the memory unit of its paired processor, or both its memory unit and the memory unit of its paired processor.
Claim 14
Dependent Claim
337 words
A multiprocessor, shared memory system comprising paired processors, each processor having: (a) a memory bus; (b) a memory unit coupled to the memory bus; (c) a processor bus; (d) a processor and memory management unit coupled to the processor bus; (e) a memory-processor interface coupled to the memory bus and the processor bus, for controlling transfers of data between the memory unit and the processor and memory management unit; (f) first and second external interprocessor interfaces each coupled to respective first and second internal interprocessor busses and to respective first and second external interprocessor busses, the first and second external interprocessor busses directly coupling each processor to the corresponding first and second external interprocessor busses of its paired processor, the first and second external interprocessor bus interfaces for controlling information transfers between the respective first and second external interprocessor busses and the respective first and second internal interprocessor busses; (g) first and second internal interprocessor interfaces, each respectively coupled to the first and second internal interprocessor busses and to the processor bus, for controlling information transfers between the respective first and second internal interprocessor busses and the processor bus; (h) first and second interprocessor-memory bus interfaces each respectively coupled to the first and second internal interprocessor busses and to the memory bus for controlling information transfers between the respective first and second internal interprocessor busses and the memory bus; and (i) data comparison means coupled to receive data from the memory unit of the processor and from the corresponding memory of its paired processor, for comparing the data accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of its paired processor, and signaling an error condition if the data accessed from the paired processors are not equivalent; whereby each processor is normally active and may, in a single operation, independently access only its memory unit, only the memory unit of its paired processor, or both its memory unit and the memory unit of its paired processor.
Claim 15
Independent Claim
449 words
A method for equalizing the data contents of the memory units of a multiprocessor, shared memory system comprising at least two processors, each processor having at least two external communications paths, a memory unit having at least three ports, a processor and memory management unit coupled to the memory unit through a first port, first coupling means for independently coupling at least two ports of the memory unit to at least two of the external communications paths of another processor, second coupling means for independently coupling the processor and memory management unit to at least two of the external communications paths of another processor, data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, the method comprising the steps of: (a) operating one processor in an out-of-service mode, whereby the out-of-service processor is enabled to access the memory unit of a second processor; (b) operating the second processor in an in-service non-duplex mode, whereby the in-service processor is disabled from accessing the memory unit of the out-of-service processor but operates to execute at least one operational task; (c) copying selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (d) after all selected data is copied, switching the in-service processor to a duplex mode, whereby the in-service processor is enabled to access the memory unit of the out-of-service processor while operating to execute at least one operational task; (e) re-copying a portion of the selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (f) comparing the re-copied portion of data in the memory unit of the in-service processor with the corresponding portion of the previously copied data from the memory unit of the in-service processor, and indicating an error if the compared data is not equivalent; (g) writing data changed by the execution in the in-service processor of at least one operational task to the memory unit of the out-of-service processor; (h) repeating steps (e) through (g) until all of the selected data is re-copied into the memory unit of the out-of-service processor; (i) thereafter, operating the out-of-service processor in an in-service mode.
Claim 16
Independent Claim
449 words
A method for equalizing the data contents of the memory units of a multiprocessor, shared memory system comprising at least two processors, each processor having at least two external communications paths, a memory unit having at least three ports, a processor and memory management unit coupled to the memory unit through a first port, first coupling means for independently coupling at least two ports of the memory unit to at least two of the external communications paths of another processor, second coupling means for independently coupling the processor and memory management unit to at least two of the external communications paths of another processor, data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, the method comprising the steps of: (a) operating one processor in an out-of-service mode, whereby the out-of-service processor is enabled to access the memory unit of a second processor; (b) operating the second processor in an in-service non-duplex mode, whereby the in-service processor is disabled from accessing the memory unit of the out-of-service processor but operates to execute at least one operational task; (c) copying selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (d) after all selected data is copied, switching the in-service processor to a duplex mode, whereby the in-service processor is enabled to access the memory unit of the out-of-service processor while operating to execute at least one operational task; (e) re-copying a portion of the selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (f) comparing the re-copied portion of data in the memory unit of the in-service processor with the corresponding portion of the previously copied data from the memory unit of the in-service processor, and indicating an error if the compared data is not equivalent; (g) writing data changed by the execution in the in-service processor of at least one operational task to the memory unit of the out-of-service processor; (h) repeating steps (e) through (g) until all of the selected data is re-copied into the memory unit of the out-of-service processor; (i) thereafter, operating the out-of-service processor in an in-service mode.
Claim 17
Independent Claim
535 words
A method for equalizing the data contents of the memory units of a multiprocessor, shared memory system comprising at least two processors, each processor having at least two external communications paths, a memory unit having at least three ports, a processor and memory management unit coupled to the memory unit through a first port, first coupling means for independently coupling at least two ports of the memory unit to at least two of the external communications paths of another processor, second coupling means for independently coupling the processor and memory management unit to at least two of the external communications paths of another processor, the first coupling means controlling data accesses to the memory unit by at least one other processor, and the second coupling means controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, and signaling an error condition if the accessed data values are not equivalent, whereby each processor may independently access only its memory, only the memory of at least one other processor, or both its memory and the memory of at least one other processor, the method comprising the steps of: (a) operating one processor in an out-of-service mode, whereby the out-of-service processor is enabled to access the memory unit of a second processor; (b) operating the second processor in an in-service non-duplex mode, whereby the in-service processor is disabled from accessing the memory unit of the out-of-service processor but operates to execute at least one operational task; (c) copying selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (d) after all selected data is copied, switching the in-service processor to a duplex mode, whereby the in-service processor is enabled to access the memory unit of the out-of-service processor while operating to execute at least one operational task; (e) re-copying a portion of the selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (f) comparing the re-copied portion of data in the memory unit of the in-service processor with the corresponding portion of the previously copied data from the memory unit of the in-service processor, and indicating an error if the compared data is not equivalent; (g) writing data changed by the execution in the in-service processor of at least one operational task to the memory unit of the out-of-service processor; (h) repeating steps (e) through (g) until all of the selected data is re-copied into the memory unit of the out-of-service processor; (i) thereafter, operating the out-of-service processor in an in-service mode.
Claim 18
Independent Claim
535 words
A method for equalizing the data contents of the memory units of a multiprocessor, shared memory system comprising at least two processors, each processor having at least two external communications paths, a memory unit having at least three ports, a processor and memory management unit coupled to the memory unit through a first port, first coupling means for independently coupling at least two ports of the memory unit to at least two of the external communications paths of another processor, second coupling means for independently coupling the processor and memory management unit to at least two of the external communications paths of another processor, the first coupling means controlling data accesses to the memory unit by at least one other processor, and the second coupling means controlling data accesses by the processor and memory management unit to the memory unit of at least one other processor, data comparison means, coupled to receive at least the data values from the memory unit of the processor and from the corresponding memory of at least one other processor, for comparing data values accessed by the processor and memory management unit from the memory unit of the processor and from the corresponding memory of at least one other processor, and signaling an error condition if the accessed data values are not equivalent, whereby each processor may independently access only its memory, only the memory of at least one other processor, or both its memory and the memory of at least one other processor, the method comprising the steps of: (a) operating one processor in an out-of-service mode, whereby the out-of-service processor is enabled to access the memory unit of a second processor; (b) operating the second processor in an in-service non-duplex mode, whereby the in-service processor is disabled from accessing the memory unit of the out-of-service processor but operates to execute at least one operational task; (c) copying selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (d) after all selected data is copied, switching the in-service processor to a duplex mode, whereby the in-service processor is enabled to access the memory unit of the out-of-service processor while operating to execute at least one operational task; (e) re-copying a portion of the selected data from the memory unit of the in-service processor into the memory unit of the out-of-service processor over one of the communications paths, concurrent with the execution of at least one operational task in the in-service processor; (f) comparing the re-copied portion of data in the memory unit of the in-service processor with the corresponding portion of the previously copied data from the memory unit of the in-service processor, and indicating an error if the compared data is not equivalent; (g) writing data changed by the execution in the in-service processor of at least one operational task to the memory unit of the out-of-service processor; (h) repeating steps (e) through (g) until all of the selected data is re-copied into the memory unit of the out-of-service processor; (i) thereafter, operating the out-of-service processor in an in-service mode.
Claim 19
Dependent Claim
139 words
A multiprocessor shared memory system comprising two processors, each of the two processors having: an associated memory including first, second, and third ports; a processing unit coupled for access to the associated memory through the second of the three ports, the processing unit independently accessing its associated memory through the second port thereof; and coupling means for redundantly and directly coupling the processing unit to the memory associated with the processing unit of the other of the two processors through the first and third ports of the memory of the other processing unit, the processing unit at the same time capable of accessing the memory associated with the processing unit through the second port and of accessing the memory associated with the other processing unit through the first and third ports of the memory of the other processing unit.
Claim 20
Dependent Claim
139 words
A multiprocessor shared memory system comprising two processors, each of the two processors having: an associated memory including first, second, and third ports; a processing unit coupled for access to the associated memory through the second of the three ports, the processing unit independently accessing its associated memory through the second port thereof; and coupling means for redundantly and directly coupling the processing unit to the memory associated with the processing unit of the other of the two processors through the first and third ports of the memory of the other processing unit, the processing unit at the same time capable of accessing the memory associated with the processing unit through the second port and of accessing the memory associated with the other processing unit through the first and third ports of the memory of the other processing unit.
Claim 21
Dependent Claim
45 words
The system of claim 14, further including data comparison means coupled to the system for receiving data from the memories associated with each processing unit and for comparing the data and generating an error condition if the data accessed from the memories are not equivalent.
Claim 22
Dependent Claim
96 words
The system of claim 15, wherein the multiprocessor shared memory system functions in a duplex mode of operation, wherein the coupling means includes redundant access paths between each processing unit and the first and third ports of the memory associated with the other processing unit and, further, wherein one of the processing units of the two processors accesses the memory of the other processor over a first of the redundant access paths and the other of the processing units accesses the associated memory of the one processing unit over a second of the redundant access paths.
Claim 23
Dependent Claim
40 words
The system of claim 16, wherein each of the processing units can continue to access the memory of the other processor over one of the first and second path if the other of the first and second paths is inoperative.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |