US5495505A
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US
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Increased frequency resolution in a synthesizer
Assignee: Motorola Solutions Inc
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Filing: 1990-12-20
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Granted: 1996-02-27
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Expires: 2010-12-20
Abstract
Abstract A direct digital frequency synthesizer increases the frequency resolution of the analog output signal by using fractionalization techniques. The best integer value I FR of a digital signal is determined and the next integer value I FR +1 of a digital signal is used to determine a weighted fractionalized value of the digital signal. The fractionalized value of the digital signal is used to synthesize the analog output signal having increased frequency resolution. In addition, IFR and IFR+1 are optimally distributed during the weighting process to ensure a minimum cumulative phase error.
Inventors
- 👤 Thomas J. Kundmann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 00:26
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F1/0328
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
69 words
A frequency synthesizer having increased frequency resolution of an analog output signal, the analog output signal being synthesized in accordance with a digital control signal, the frequency synthesizer comprising: means for distributing a first digital input signal for a first fractional interval N and a second digital input signal for a second fractional interval D-N; and means, coupled to said means for distributing, for synthesizing the analog output signal.
Claim 2
Dependent Claim
69 words
A frequency synthesizer having increased frequency resolution of an analog output signal, the analog output signal being synthesized in accordance with a digital control signal, the frequency synthesizer comprising: means for distributing a first digital input signal for a first fractional interval N and a second digital input signal for a second fractional interval D-N; and means, coupled to said means for distributing, for synthesizing the analog output signal.
Claim 3
Dependent Claim
56 words
The frequency synthesizer of claim 1 wherein said means for distributing comprises means for providing the first digital input signal having an integer value representing a first phase error for the first fractional interval N and the second digital input signal having an integer value representing a second phase error for the second fractional interval D-N.
Claim 4
Dependent Claim
30 words
The frequency synthesizer of claim 2 wherein said means for synthesizing comprises means for accumulating said first phase error and said second phase error to produce an accumulated phase error.
Claim 5
Dependent Claim
34 words
The frequency synthesizer of claim 3 wherein said means for synthesizing further comprises means for distributing the accumulation of said first phase error and said second phase error to minimize said accumulated phase error.
Claim 6
Dependent Claim
100 words
A frequency synthesizer having increased frequency resolution of an analog output signal, the analog output signal being synthesized in accordance with a digital input signal, the frequency synthesizer comprising: means for generating a first integer value for a first fractional interval N and for generating a second integer value for a second fractional interval D-N based on the digital input signal and for generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; and means, coupled to said means for generating the weighted average, for synthesizing the analog output signal.
Claim 7
Dependent Claim
100 words
A frequency synthesizer having increased frequency resolution of an analog output signal, the analog output signal being synthesized in accordance with a digital input signal, the frequency synthesizer comprising: means for generating a first integer value for a first fractional interval N and for generating a second integer value for a second fractional interval D-N based on the digital input signal and for generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; and means, coupled to said means for generating the weighted average, for synthesizing the analog output signal.
Claim 8
Dependent Claim
67 words
The frequency synthesizer of claim 5 wherein said means for generating the first integer value for the first fractional interval N and the second integer value for the second fractional interval D-N comprises means for generating the first integer value representing a first phase error for the first fractional interval N and the second integer value representing a second phase error for the second fractional interval D-N.
Claim 9
Dependent Claim
30 words
The frequency synthesizer of claim 6 wherein said means for synthesizing comprises means for accumulating said first phase error and said second phase error to produce an accumulated phase error.
Claim 10
Dependent Claim
34 words
The frequency synthesizer of claim 7 wherein said means for synthesizing further comprises means for distributing the accumulation of said first phase error and said second phase error to minimize said accumulated phase error.
Claim 11
Dependent Claim
117 words
A transmitter incorporating a direct digital frequency synthesizer which synthesizes an analog output signal, the transmitter comprising: means for generating a first integer value for a first fractional interval and for generating a second integer value for a second fractional interval based on a digital input signal corresponding to a frequency of the analog output signal and for generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; means, coupled to said means for generating the weighted average, for synthesizing the analog output signal; and means, coupled to said means for synthesizing, for transmitting a radio frequency signal having a frequency related to said analog output signal.
Claim 12
Dependent Claim
117 words
A transmitter incorporating a direct digital frequency synthesizer which synthesizes an analog output signal, the transmitter comprising: means for generating a first integer value for a first fractional interval and for generating a second integer value for a second fractional interval based on a digital input signal corresponding to a frequency of the analog output signal and for generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; means, coupled to said means for generating the weighted average, for synthesizing the analog output signal; and means, coupled to said means for synthesizing, for transmitting a radio frequency signal having a frequency related to said analog output signal.
Claim 13
Dependent Claim
62 words
The transmitter of claim 9 wherein said means for generating the first integer value for the first fractional interval and the second integer value for the second fractional interval comprises means for generating the first integer value representing a first phase error for the first fractional interval and the second integer value representing a second phase error for the second fractional interval.
Claim 14
Dependent Claim
29 words
The transmitter of claim 10 wherein said means for synthesizing comprises means for accumulating said first phase error and said second phase error to produce an accumulated phase error.
Claim 15
Dependent Claim
39 words
The transmitter of claim 11 wherein said means for synthesizing further comprises means, responsive to said means for accumulating, for distributing the accumulation of said first phase error and said second phase error to minimize said accumulated phase error.
Claim 16
Dependent Claim
87 words
The transmitter of claim 9 wherein said means for generating the first integer value for the first fractional interval and for generating the second integer value for the second fractional interval based on the digital input signal corresponding to the frequency of the analog output signal comprises means for generating the first integer value for the first fractional interval and for generating the second integer value for the second fractional interval based on the digital input signal corresponding to the modulation requirements of the analog output signal.
Claim 17
Independent Claim
82 words
A method of increasing the frequency resolution of an analog output signal in a frequency synthesizer, the analog output signal being synthesized in accordance with a digital control signal, the method comprising the steps of: providing a first digital input signal for a first fractional interval N and a second digital input signal for a second fractional interval D-N; and distributing said first digital input signal and said second digital input signal over D fractional intervals to produce the digital control signal.
Claim 18
Independent Claim
82 words
A method of increasing the frequency resolution of an analog output signal in a frequency synthesizer, the analog output signal being synthesized in accordance with a digital control signal, the method comprising the steps of: providing a first digital input signal for a first fractional interval N and a second digital input signal for a second fractional interval D-N; and distributing said first digital input signal and said second digital input signal over D fractional intervals to produce the digital control signal.
Claim 19
Dependent Claim
79 words
The method of claim 14 wherein said step of providing the first digital input signal for the first fractional interval N and the second digital input signal for the second fractional interval D-N comprises the step of providing the first digital input signal having an integer value representing a first phase error for the first fractional interval N and the second digital input signal having an integer value representing a second phase error for the second fractional interval D-N.
Claim 20
Dependent Claim
30 words
The method of claim 15 wherein said step of distributing comprises the step of accumulating said first phase error and said second phase error to produce an accumulated phase error.
Claim 21
Dependent Claim
40 words
The method of claim 16 wherein said step of distributing further comprises the step, responsive to said step of accumulating, of distributing the accumulation of said first phase error and said second phase error to minimize said accumulated phase error.
Claim 22
Independent Claim
115 words
A method of increasing the frequency resolution of an analog output signal in a frequency synthesizer, the analog output signal being synthesized in accordance with a digital input signal, the method comprising the steps of: generating a first integer value for a first fractional interval N and generating a second integer value for a second fractional interval D-N based on the digital input signal; generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; providing a reference signal having a fixed frequency; and synthesizing, based on said step of generating the weighted average and said step of providing the reference signal, the analog output signal.
Claim 23
Independent Claim
115 words
A method of increasing the frequency resolution of an analog output signal in a frequency synthesizer, the analog output signal being synthesized in accordance with a digital input signal, the method comprising the steps of: generating a first integer value for a first fractional interval N and generating a second integer value for a second fractional interval D-N based on the digital input signal; generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; providing a reference signal having a fixed frequency; and synthesizing, based on said step of generating the weighted average and said step of providing the reference signal, the analog output signal.
Claim 24
Dependent Claim
67 words
The method of claim 18 wherein said step of generating the first integer value for the first fractional interval N and the second integer value for the second fractional interval D-N comprises the step of generating the first integer value representing a first phase error for the first fractional interval N and the second integer value representing a second phase error for the second fractional interval D-N.
Claim 25
Dependent Claim
30 words
The method of claim 19 wherein said step of synthesizing comprises the step of accumulating said first phase error and said second phase error to produce an accumulated phase error.
Claim 26
Dependent Claim
41 words
The method of claim 20 wherein said step of synthesizing further comprises the step, responsive to said the step of accumulating, of distributing the accumulation of said first phase error and said second phase error to minimize said accumulated phase error.
Claim 27
Independent Claim
123 words
A method of synthesizing an analog output signal in a frequency synthesizer incorporated in a transmitter, the method comprising the steps of: generating a first integer value for a first fractional interval and a second integer value for a second fractional interval based on a digital input signal corresponding to a frequency of the analog output signal; generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; providing a reference signal having a fixed frequency; synthesizing, based on said step of generating the weighted average and said step of providing the reference signal, the analog output signal; and transmitting a radio frequency signal having a frequency related to said synthesized analog output signal.
Claim 28
Independent Claim
123 words
A method of synthesizing an analog output signal in a frequency synthesizer incorporated in a transmitter, the method comprising the steps of: generating a first integer value for a first fractional interval and a second integer value for a second fractional interval based on a digital input signal corresponding to a frequency of the analog output signal; generating a weighted average of said first integer value and said second integer value to produce a first non-integer value; providing a reference signal having a fixed frequency; synthesizing, based on said step of generating the weighted average and said step of providing the reference signal, the analog output signal; and transmitting a radio frequency signal having a frequency related to said synthesized analog output signal.
Claim 29
Dependent Claim
63 words
The method of claim 22 wherein said step of generating the first integer value for the first fractional interval and the second integer value for the second fractional interval comprises the step of generating the first integer value representing a first phase error for the first fractional interval and the second integer value representing a second phase error for the second fractional interval.
Claim 30
Dependent Claim
30 words
The method of claim 23 wherein said step of synthesizing comprises the step of accumulating said first phase error and said second phase error to produce an accumulated phase error.
Claim 31
Dependent Claim
41 words
The method of claim 24 wherein said step of synthesizing further comprises the step, responsive to said the step of accumulating, of distributing the accumulation of said first phase error and said second phase error to minimize said accumulated phase error.
Claim 32
Dependent Claim
88 words
The method of claim 22 wherein said step of generating the first integer value for the first fractional interval and for generating the second integer value for the second fractional interval based on the distal input signal corresponding to the frequency of the analog output signal comprises the step of generating a first integer value for the first fractional interval and for generating a second integer value for the second fractional interval based on the digital input signal corresponding to the modulation requirements of the analog output signal.
References Cited (Backward Citations)
US4053739A
Cited
US4179670A
Cited
US4204174A
Cited
US4758802A
Cited
US4800342A
Cited
US4893316A
Cited
US4815018A
Cited
US4962510A
Cited
US4901265A
Cited
WO1990006624A1
Cited
US4984186A
Cited
US5073869A
Cited
US4965533A
Cited
US4965531A
Cited
US5122762A
Cited
US4998072A
Cited
EP0459446A1
Cited
US5045817A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |