US4965533A
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US
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Direct digital synthesizer driven phase lock loop frequency synthesizer
Assignee: Qualcomm Inc
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Filing: 1989-08-31
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Granted: 1990-10-23
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Expires: 2009-08-31
Abstract
Abstract A frequency synthesizer which uses a direct digital synthesizer (DDS) to drive a phase lock loop. The DDS generates a highly accurate periodic signal of a frequency selected from a plurality of reference frequencies. A phase lock loop receives the DDS generated reference signal and a divide-by-N signal for generating an output signal at a frequency determined by the divide-by-N signal. The frequency resolution of the phase lock loop is N times the reference signal. In a second embodiment, the DDS is incorporated within the feedback path of the phase lock loop. An input reference frequency signal is provided to the phase lock loop with the DDS clock signal provided as a function of the phase lock loop output frequency. The DDS receives an input frequency control signal which determines the DDS step size. The synthesizer output frequency is a function of the input reference , the number of bits in the digital word of the frequency control signal and the DDS step size as determined by the frequency control signal. Optional dividers may be provided in the feedback path which may further affect the synthesizer output frequency.
Inventors
- 👤 Robert P. Gilmore
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 01:49
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/1806
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
187 words
An apparatus for synthesizing frequencies, comprising: variable reference means for generating a periodic signal of a frequency selected from a plurality of reference frequencies, said variable reference means comprising, phase accumulator means for, receiving a digital frequency control signal indicative of a selected phase increment value, receiving an externally generated clock signal, accumulating phase increment values at a rate corresponding to said clock signal, and providing an accumulator output signal corresponding to said accumulated phase increment values; memory means for storing a plurality of amplitude values each corresponding to a respective accumulated phase increment value, receiving said accumulator output signal and providing a memory output signal indicative of the amplitude value corresponding to each accumulated phase increment value of said accumulator output signal; and converter means for, receiving said memory output signal converting said received memory output signal to an analog amplitude signal corresponding to said memory output signal amplitude values, and providing said analog amplitude signal as said periodic signal; and frequency tuning means for receiving said periodic signal and generating an output signal of a frequency which is a multiple of said periodic signal frequency.
Claim 2
Independent Claim
187 words
An apparatus for synthesizing frequencies, comprising: variable reference means for generating a periodic signal of a frequency selected from a plurality of reference frequencies, said variable reference means comprising, phase accumulator means for, receiving a digital frequency control signal indicative of a selected phase increment value, receiving an externally generated clock signal, accumulating phase increment values at a rate corresponding to said clock signal, and providing an accumulator output signal corresponding to said accumulated phase increment values; memory means for storing a plurality of amplitude values each corresponding to a respective accumulated phase increment value, receiving said accumulator output signal and providing a memory output signal indicative of the amplitude value corresponding to each accumulated phase increment value of said accumulator output signal; and converter means for, receiving said memory output signal converting said received memory output signal to an analog amplitude signal corresponding to said memory output signal amplitude values, and providing said analog amplitude signal as said periodic signal; and frequency tuning means for receiving said periodic signal and generating an output signal of a frequency which is a multiple of said periodic signal frequency.
Claim 3
Dependent Claim
123 words
The apparatus of claim 1 wherein said frequency tuning means comprises: phase detector means for, receiving said periodic signal and a feedback signal, detecting a phase difference between said periodic signal and said feedback signal and providing a corresponding error signal: loop filter means for, receiving said error signal, filtering noise in said error signal, and providing a filtered error signal as a control signal; variable oscillator means for receiving said control signal and responsive thereto for generating said output signal; divider means for receiving said output signal dividing said output signal frequency by N, and providing said feedback signal corresponding in frequency to said output signal frequency divided by N, wherein said output signal frequency is N times said periodic signal frequency.
Claim 4
Dependent Claim
46 words
The apparatus of claim 1 further comprising filter means, disposed between said variable reference means and said frequency tuning means, for receiving said periodic signal, enhancing the spectral purity of said periodic signal and providing said spectral purity enhanced periodic signal to said frequency tuning means.
Claim 5
Dependent Claim
45 words
The apparatus of claim 2 further comprising filter means, disposed between said converter means and said phase detector means, for receiving said periodic signal, enhancing the spectral purity of said periodic signal and providing said spectral purity enhanced periodic signal to said phase detector means.
Claim 6
Dependent Claim
64 words
The apparatus of claim 4 further comprising additional divider means disposed between said filter means and said phase detector means for receiving said spectral purity enhanced periodic signal and providing to said phase detector means a divided frequency periodic signal corresponding in frequency to said periodic signal frequency divided by M, said output signal frequency being N times said divided frequency periodic signal frequency.
Claim 7
Dependent Claim
107 words
A frequency synthesizer comprising: a direct digital synthesizer (DDS) having, a fine frequency control input and a DDS clock input for respectively receiving externally generated phase data and an externally generated clock signal, and an output at which a reference signal is provided; a filter having an input, coupled to said DDS output, and an output; and a phase lock loop having a loop input coupled to said filter output, a coarse frequency control input for receiving a divide-by-N signal, and a loop output wherein said loop provides at said loop output a synthesizer output signal of a frequency N times the frequency of said reference signal.
Claim 8
Dependent Claim
107 words
A frequency synthesizer comprising: a direct digital synthesizer (DDS) having, a fine frequency control input and a DDS clock input for respectively receiving externally generated phase data and an externally generated clock signal, and an output at which a reference signal is provided; a filter having an input, coupled to said DDS output, and an output; and a phase lock loop having a loop input coupled to said filter output, a coarse frequency control input for receiving a divide-by-N signal, and a loop output wherein said loop provides at said loop output a synthesizer output signal of a frequency N times the frequency of said reference signal.
Claim 9
Dependent Claim
64 words
The synthesizer of claim 6 further comprising a frequency divider, disposed between said filter and said phase lock loop, having an input coupled to said filter output and an output coupled to said loop input, said frequency divider for dividing said reference signal frequency by M with said phase lock loop having a frequency of N times said reference signal frequency divided by M.
Claim 10
Dependent Claim
102 words
The synthesizer of claim 6 wherein said direct digital synthesizer comprises: a phase accumulator having a phase data input for receiving said phase data, an accumulator clock input for receiving said clock signal, and an accumulator output; a read only memory having a plurality of addressable storage locations each storing a predetermined sine value, an address input coupled to said accumulator output, a memory clock input for receiving said clock signal and a memory output; a digital to analog converter having a converter input coupled to said memory output, a converter clock input for receiving said clock signal and a converter output.
Claim 11
Dependent Claim
110 words
The frequency synthesizer of claim 6 wherein said phase lock loop comprises: a phase detector having a reference input coupled to said filter output, a feedback input and a detector output; a loop filter having a loop filter input, coupled to said detector output, and a loop filter output; a voltage controlled oscillator having a control input, coupled to said loop filter output, and an oscillator output, said synthesizer output signal being provided at said oscillator output; and a variable frequency divider having a divider input coupled to said oscillator output, a divider control input for receiving said divide-by-N signal, and a divider output coupled to said detector feedback input.
Claim 12
Dependent Claim
110 words
The frequency synthesizer of claim 8 wherein said phase lock loop comprises: a phase detector having a reference input coupled to said filter output, a feedback input and a detector output; a loop filter having a loop filter input coupled to said detector output and a loop filter output; a voltage controlled oscillator having a control input, coupled to said loop filter output, and an oscillator output, said synthesizer output signal being provided at said oscillator output; and a variable frequency divider having a divider input coupled to said oscillator output, a divider control input for receiving said divide-by-N signal, and a divider output coupled to said detector feedback input.
Claim 13
Dependent Claim
56 words
The synthesizer of claim 10 further comprising a frequency divider, disposed between said filter and said phase lock loop, having an output coupled to said reference input, said frequency divider dividing said reference signal frequency by M, with said synthesizer output signal being of a frequency of N times said reference signal frequency divided by M.
Claim 14
Dependent Claim
116 words
A phase lock loop frequency synthesizer comprising: a phase detector having a reference input for receiving an externally generated reference signal of a predetermined frequency, a feedback input and an output; a loop filter having an input, coupled to said detector output, and an output; a voltage controlled oscillator having an input, coupled to said loop filter output, and an output for providing a synthesizer output signal; a direct digital synthesizer (DDS) having a DDS clock input coupled to said oscillator output, a frequency control input for receiving externally generated phase data, and an output; and a bandpass filter having an input coupled to said DDS output and an output coupled to said detector feedback input.
Claim 15
Dependent Claim
116 words
A phase lock loop frequency synthesizer comprising: a phase detector having a reference input for receiving an externally generated reference signal of a predetermined frequency, a feedback input and an output; a loop filter having an input, coupled to said detector output, and an output; a voltage controlled oscillator having an input, coupled to said loop filter output, and an output for providing a synthesizer output signal; a direct digital synthesizer (DDS) having a DDS clock input coupled to said oscillator output, a frequency control input for receiving externally generated phase data, and an output; and a bandpass filter having an input coupled to said DDS output and an output coupled to said detector feedback input.
Claim 16
Dependent Claim
109 words
The synthesizer of claim 12 wherein said direct digital synthesizer comprises: a phase accumulator having a phase data input for receiving said phase data, an accumulator clock input coupled to said oscillator output, and an accumulator output; a read only memory having a plurality of addressable storage locations each storing a predetermined sine value, an address input coupled to said accumulator for output, a memory clock input coupled to said oscillator output and a memory output; a digital to analog converter having a converter input coupled to said memory output, a converter clock input coupled to said oscillator output, and a converter output coupled to said bandpass filter input.
Claim 17
Dependent Claim
54 words
The synthesizer of claim 12 further comprising a first loop divider, disposed between said oscillator and said DDS, having an input coupled to said oscillator output and an output coupled to said DDS clock input, said first loop divider dividing said synthesizer output signal frequency by X as provided to said DDS clock input.
Claim 18
Dependent Claim
58 words
The synthesizer of claim 12 further comprising a loop divider, disposed between said bandpass filter and said phase detector, having an input coupled to said bandpass filter output and an output coupled to said detector feedback input, said loop divider dividing a signal output from said DDS in frequency by Y for providing to said detector feedback input.
Claim 19
Dependent Claim
60 words
The synthesizer of claim 14 further comprising a second loop divider, disposed between said bandpass filter and said phase detector, having an input coupled to said bandpass filter output and an output coupled to said detector feedback input, said second loop divider dividing a signal output from said DDS in frequency by Y for providing to said detector feedback input.
Claim 20
Independent Claim
153 words
A method for synthesizing frequency comprising the steps of: providing a direct digital synthesizer (DDS) capable of generating an analog DDS output signal at a frequency selected from a plurality of frequencies; providing externally generated phase data and clock signals to said DDS; generating in said DDS, in response to an input of said phase data and said clock signal, a DDS analog output signal having a frequency corresponding to said phase data; providing a phase lock loop capable of generating a loop output signal at a frequency corresponding to an input reference signal and a divide-by-N signal; providing to said phase lock loop, said DDS output signal as said reference signal, and said divide-by-N signal; and generating in said phase lock loop, in response to said input of said DDS output signal and said divide-by-N signal, said loop output signal corresponding in frequency to a multiple of aid generated DDS output signal.
Claim 21
Independent Claim
153 words
A method for synthesizing frequency comprising the steps of: providing a direct digital synthesizer (DDS) capable of generating an analog DDS output signal at a frequency selected from a plurality of frequencies; providing externally generated phase data and clock signals to said DDS; generating in said DDS, in response to an input of said phase data and said clock signal, a DDS analog output signal having a frequency corresponding to said phase data; providing a phase lock loop capable of generating a loop output signal at a frequency corresponding to an input reference signal and a divide-by-N signal; providing to said phase lock loop, said DDS output signal as said reference signal, and said divide-by-N signal; and generating in said phase lock loop, in response to said input of said DDS output signal and said divide-by-N signal, said loop output signal corresponding in frequency to a multiple of aid generated DDS output signal.
Claim 22
Dependent Claim
19 words
The method of claim 17 further comprising the step of enhancing the spectral purity of said DDS output signal.
Claim 23
Dependent Claim
52 words
The method of claim 17 further comprising the steps of: dividing said DDS output signal frequency; and providing said divided frequency DDS output signal to said phase lock loop wherein said phase lock loop generates loop output signals at a frequency of N times said DDS output signal frequency divided by M.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-22 | 1994-04-23 | 1994-10-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-22 | 1998-04-23 | 1998-10-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-22 | 2002-04-23 | 2002-10-23 | $7700.00 | Window Closed / Lapsed |