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US5495452A
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Circuit for controlling a self-refresh period in a semiconductor memory device
Assignee: Samsung Electronics Co Ltd
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Filing: 1994-07-14
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Granted: 1996-02-27
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Expires: 2014-07-14
Abstract
Abstract A circuit which controls a self-refresh period of a semiconductor memory device includes a pulse generating circuit which outputs a periodic pulse train in response to an external control signal, a frequency-dividing circuit which outputs a plurality of pulse trains having different respective periods by frequency-dividing the pulse train, at least one temperature detector which detects an ambient temperature of the memory device and outputs a temperature detection signal when the ambient temperature exceeds a predetermined threshold level, at least one voltage detecting circuit which detects a power supply voltage applied to the memory device and outputs a voltage detection signal when the power supply voltage reaches a predetermined level, a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining the plurality of pulse trains output by the frequency-dividing circuit, and a pulse selecting circuit which outputs a self-refresh master clock by selecting one of the combination pulse trains in response to the voltage detection signal and the temperature detection signal.
Inventors
- 👤 Gi-Won Cha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:30
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G11C11/40615; G11C11/40626
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
149 words
A period control circuit for self-refresh operation in a semiconductor memory device comprising: pulse generating means for outputting a predetermined periodic pulse train in response to an external control signal; frequency-dividing means for outputting a plurality of pulse trains which have different periods from each other by frequency-dividing said pulse train output from said pulse generating means; at least one temperature detecting means for detecting an ambient temperature of said memory device and for outputting a temperature detection signal when said ambient temperature reaches a predetermined level; at least one voltage detecting means for detecting a power supply voltage applied to said memory device and for outputting a voltage detection signal when said power supply voltage reaches a predetermined level; and pulse selecting means for outputting a self-refresh master clock by selecting one of said pulse trains in response to said voltage detection signal and said temperature detection signal.
Claim 2
Dependent Claim
149 words
A period control circuit for self-refresh operation in a semiconductor memory device comprising: pulse generating means for outputting a predetermined periodic pulse train in response to an external control signal; frequency-dividing means for outputting a plurality of pulse trains which have different periods from each other by frequency-dividing said pulse train output from said pulse generating means; at least one temperature detecting means for detecting an ambient temperature of said memory device and for outputting a temperature detection signal when said ambient temperature reaches a predetermined level; at least one voltage detecting means for detecting a power supply voltage applied to said memory device and for outputting a voltage detection signal when said power supply voltage reaches a predetermined level; and pulse selecting means for outputting a self-refresh master clock by selecting one of said pulse trains in response to said voltage detection signal and said temperature detection signal.
Claim 3
Dependent Claim
173 words
A period control circuit for self-refresh operation in a semiconductor memory device comprising: pulse generating means for outputting a predetermined periodic pulse train in response to an external control signal; frequency-dividing means for outputting a plurality of pulse trains which have different periods from each other by frequency-dividing said pulse train output from said pulse generating means; at least one temperature detecting means for detecting an ambient temperature of said memory device and for outputting a temperature detection signal when said ambient temperature reaches a predetermined level; at least one voltage detecting means for detecting a power supply voltage applied to said memory device and for outputting a voltage detection signal when said power supply voltage reaches a predetermined level; combination pulse train generating means for outputting a plurality of combination pulse trains by combining said pulse trains output from said frequency-dividing means; and pulse selecting means for outputting a self-refresh master clock by selecting one of said combination pulse trains in response to said voltage detection signal and said temperature detection signal.
Claim 4
Dependent Claim
173 words
A period control circuit for self-refresh operation in a semiconductor memory device comprising: pulse generating means for outputting a predetermined periodic pulse train in response to an external control signal; frequency-dividing means for outputting a plurality of pulse trains which have different periods from each other by frequency-dividing said pulse train output from said pulse generating means; at least one temperature detecting means for detecting an ambient temperature of said memory device and for outputting a temperature detection signal when said ambient temperature reaches a predetermined level; at least one voltage detecting means for detecting a power supply voltage applied to said memory device and for outputting a voltage detection signal when said power supply voltage reaches a predetermined level; combination pulse train generating means for outputting a plurality of combination pulse trains by combining said pulse trains output from said frequency-dividing means; and pulse selecting means for outputting a self-refresh master clock by selecting one of said combination pulse trains in response to said voltage detection signal and said temperature detection signal.
Claim 5
Dependent Claim
147 words
A circuit for controlling a self-refresh period of a semiconductor memory device, comprising: a pulse generating circuit which outputs a periodic pulse train in response to an external control signal; a frequency-dividing circuit which outputs a plurality of pulse trains having different periods from each other by frequency-dividing said periodic pulse train output by said pulse generating circuit; a temperature detection circuit which detects an ambient temperature of said memory device and outputs a temperature detection signal when said ambient temperature reaches a predetermined temperature level; a voltage detection circuit which detects a power supply voltage applied to said memory device and outputs a voltage detection signal when said power supply voltage reaches a predetermined voltage level; and, a pulse selection circuit which outputs a self-refresh master clock by selecting one of said pulse trains in response to said temperature detection signal and said voltage detection signal.
Claim 6
Dependent Claim
147 words
A circuit for controlling a self-refresh period of a semiconductor memory device, comprising: a pulse generating circuit which outputs a periodic pulse train in response to an external control signal; a frequency-dividing circuit which outputs a plurality of pulse trains having different periods from each other by frequency-dividing said periodic pulse train output by said pulse generating circuit; a temperature detection circuit which detects an ambient temperature of said memory device and outputs a temperature detection signal when said ambient temperature reaches a predetermined temperature level; a voltage detection circuit which detects a power supply voltage applied to said memory device and outputs a voltage detection signal when said power supply voltage reaches a predetermined voltage level; and, a pulse selection circuit which outputs a self-refresh master clock by selecting one of said pulse trains in response to said temperature detection signal and said voltage detection signal.
Claim 7
Dependent Claim
172 words
A circuit for controlling a self-refresh period of a semiconductor memory device, comprising: a pulse generating circuit which outputs a periodic pulse train in response to an external control signal; a frequency-dividing circuit which outputs a plurality of pulse trains having different periods from each other by frequency-dividing said periodic pulse train output by said pulse generating circuit; a temperature detection circuit which detects an ambient temperature of said memory device and outputs a temperature detection signal when said ambient temperature reaches a predetermined temperature level; a voltage detection circuit which detects a power supply voltage applied to said memory device and outputs a voltage detection signal when said power supply voltage reaches a predetermined voltage level; a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining said pulse trains output by said frequency-dividing means; a pulse selection circuit which outputs a self-refresh master clock by selecting one of said combination pulse trains in response to said temperature detection signal and said voltage detection signal.
Claim 8
Dependent Claim
172 words
A circuit for controlling a self-refresh period of a semiconductor memory device, comprising: a pulse generating circuit which outputs a periodic pulse train in response to an external control signal; a frequency-dividing circuit which outputs a plurality of pulse trains having different periods from each other by frequency-dividing said periodic pulse train output by said pulse generating circuit; a temperature detection circuit which detects an ambient temperature of said memory device and outputs a temperature detection signal when said ambient temperature reaches a predetermined temperature level; a voltage detection circuit which detects a power supply voltage applied to said memory device and outputs a voltage detection signal when said power supply voltage reaches a predetermined voltage level; a combination pulse train generating circuit which outputs a plurality of combination pulse trains by variously combining said pulse trains output by said frequency-dividing means; a pulse selection circuit which outputs a self-refresh master clock by selecting one of said combination pulse trains in response to said temperature detection signal and said voltage detection signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |