US5365487A
Expired / Lapsed
US
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DRAM power management with self-refresh
Assignee: Texas Instruments Inc
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Filing: 1992-03-24
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Granted: 1994-11-15
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Expires: 2012-03-24
Abstract
Abstract A DRAM furnishes power management circuits that remove power from circuits on the DRAM that are not necessary for self-refresh and that turn on and off other circuits necessary for self-refresh in timed relation to the refresh cycle. The power management circuits include a counter and simple decoder circuits that decode the binary output of the counter.
Inventors
- 👤 Vipul C. Patel
- 👤 David R. Brown
- 👤 Jim C. Tso
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 00:30
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/14; G11C5/143; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
194 words
A computer system comprising: a central processor that performs the processing of the computer system; a memory including the data to be processed by the processor and the instructions to be used in the central processor for processing the data; a memory controller associated with the central processor for controlling access of the memory by the central processor, said memory controller producing signals indicating a sleep mode to the memory; and the memory including dynamic random access memory parts including arrays of memory cells, the cells being dynamic and requiting refresh of groups of cells at a certain rate to maintain data stored in the cells, the dynamic random access memory parts further including first circuits required to operate to support refresh of the memory cells and second circuits that can have power removed during refresh of the memory cells, the dynamic random access memory parts further including power management circuits that operate in response to the signals indicating a sleep mode to effect a self-refresh of the memory cells with operation of the first circuits substantially only at refresh of a group of cells and with electrical power removed from the second circuits.
Claim 2
Dependent Claim
194 words
A computer system comprising: a central processor that performs the processing of the computer system; a memory including the data to be processed by the processor and the instructions to be used in the central processor for processing the data; a memory controller associated with the central processor for controlling access of the memory by the central processor, said memory controller producing signals indicating a sleep mode to the memory; and the memory including dynamic random access memory parts including arrays of memory cells, the cells being dynamic and requiting refresh of groups of cells at a certain rate to maintain data stored in the cells, the dynamic random access memory parts further including first circuits required to operate to support refresh of the memory cells and second circuits that can have power removed during refresh of the memory cells, the dynamic random access memory parts further including power management circuits that operate in response to the signals indicating a sleep mode to effect a self-refresh of the memory cells with operation of the first circuits substantially only at refresh of a group of cells and with electrical power removed from the second circuits.
Claim 3
Dependent Claim
16 words
The computer system of claim 1, wherein said group of cells is a row of cells.
Claim 4
Dependent Claim
17 words
The computer system of claim 1, wherein said first circuits include dummy cell reference voltage generator circuits.
Claim 5
Dependent Claim
17 words
The computer system of claim 1, wherein said first circuits include bit line reference voltage generator circuits.
Claim 6
Dependent Claim
14 words
The computer system of claim 1, wherein said first circuits include Vbb pump circuits.
Claim 7
Dependent Claim
15 words
The computer system of claim 1, wherein said second circuits include shallow Vbb detector circuits.
Claim 8
Dependent Claim
15 words
The computer system of claim 1, wherein said second circuits include deep Vbb detector circuits.
Claim 9
Dependent Claim
14 words
The computer system of claim 1, wherein said second circuits include overvoltage detector circuits.
Claim 10
Dependent Claim
14 words
The computer system of claim 1, wherein said second circuits include column path circuits.
Claim 11
Dependent Claim
88 words
The computer system of claim 1, wherein said power management circuits include a binary counter producing binary signals, first and second decoder circuits both decoding the binary signals and each producing a respective output signal, and a dual frequency oscillator producing a clock signal applied to the binary counter and receiving the output of the second decoder circuits to indicate one of the dual frequencies, the output of the first decoder circuits controlling the first circuits and the output of the second decoder circuits controlling the second circuits.
Claim 12
Dependent Claim
35 words
The computer system of claim 1, wherein the power management circuits remove power from the second circuits about ten microseconds after recognizing a CBR refresh with an absence of RAS -- in an active state.
Claim 13
Dependent Claim
41 words
The computer system of claim 1, wherein the power management circuits operate the first circuits to support refresh of the memory cells about one hundred microseconds after recognizing a CBR refresh with an absence of RAS -- in an active state.
Claim 14
Dependent Claim
43 words
The computer system of claim 1, wherein the power management circuits cause production of an internal refresh pulse for refreshing the group of memory cells and the power management circuits produce Vbb pump signals once before and once after the internal refresh pulse.
Claim 15
Dependent Claim
50 words
The computer system of claim 1, wherein the power management circuits cause production of an internal refresh pulse for refreshing the group of memory cells and the power management circuits operating the first circuits selectably before and selectably after the internal refresh pulse to refresh of a group of cells.
Claim 16
Dependent Claim
51 words
The computer system of claim 1, wherein the second circuits are connected between Vdd and Vss supply leads and the power management circuits include a switch circuit for each of the second circuits switching the Vdd connection to another Vss supply lead to remove power from each of the second circuit.
Claim 17
Dependent Claim
32 words
The computer system of claim 1, wherein the computer system includes keyboard control circuits, display control circuits, disk drive circuits and ROM circuits connected to the central processing unit and memory circuits.
Claim 18
Dependent Claim
127 words
A dynamic random access memory part furnishing a self-refresh mode, the part comprising: an overall array of dynamic memory cells needing refresh to maintain stored data and configured in subarrays of cells connected together in rows and columns; first circuits coupled to the overall array of dynamic memory cells required to operate to support refresh of the dynamic memory cells; second circuits coupled to the overall array of dynamic memory cells and that can have power removed during refresh of the memory cells; and power management circuits connected to the first and second circuits to effect a self-refresh of the dynamic memory cells with operation of the first circuits substantially only at refresh of a row of cells and with electrical power removed from the second circuits.
Claim 19
Dependent Claim
127 words
A dynamic random access memory part furnishing a self-refresh mode, the part comprising: an overall array of dynamic memory cells needing refresh to maintain stored data and configured in subarrays of cells connected together in rows and columns; first circuits coupled to the overall array of dynamic memory cells required to operate to support refresh of the dynamic memory cells; second circuits coupled to the overall array of dynamic memory cells and that can have power removed during refresh of the memory cells; and power management circuits connected to the first and second circuits to effect a self-refresh of the dynamic memory cells with operation of the first circuits substantially only at refresh of a row of cells and with electrical power removed from the second circuits.
Claim 20
Dependent Claim
20 words
The dynamic random access memory part of claim 17, wherein said first circuits include dummy cell reference voltage generator circuits.
Claim 21
Dependent Claim
20 words
The dynamic random access memory part of claim 17, wherein said first circuits include bit line reference voltage generator circuits.
Claim 22
Dependent Claim
17 words
The dynamic random access memory part of claim 17, wherein said first circuits include Vbb pump circuits.
Claim 23
Dependent Claim
18 words
The dynamic random access memory part of claim 17, wherein said second circuits include shallow Vbb detector circuits.
Claim 24
Dependent Claim
18 words
The dynamic random access memory part of claim 17, wherein said second circuits include deep Vbb detecter circuits.
Claim 25
Dependent Claim
17 words
The dynamic random access memory part of claim 17, wherein said second circuits include overvoltage detector circuits.
Claim 26
Dependent Claim
17 words
The dynamic random access memory part of claim 17, wherein said second circuits include column path circuits.
Claim 27
Dependent Claim
99 words
The dynamic random access memory part of claim 17, wherein said power management circuits include a binary counter producing binary signals, first and second decoder circuits both decoding the binary signals and each of said first and second decoder circuits producing a respective output signal, and a dual frequency oscillator producing a clock signal applied to the binary counter and receiving the output of the second decoder signal circuits to indicate one of the dual frequencies, the output of the first decoder circuits controlling the first circuits and the output of the second decoder circuits controlling the second circuits.
Claim 28
Dependent Claim
42 words
The dynamic random access memory part of claim 17, wherein the power management circuits remove power from the second circuits about ten microseconds after recognizing a CBR refresh applied to the part with an absence of RAS -- in an active state.
Claim 29
Dependent Claim
48 words
The dynamic random access memory part of claim 17, wherein the power management circuits operate the first circuits to support refresh of the memory cells about one hundred microseconds after recognizing a CBR refresh applied to the part with an absence of RAS -- in an active state.
Claim 30
Dependent Claim
46 words
The dynamic random access memory part of claim 17, wherein the power management circuits cause production of an internal refresh pulse for refreshing the row of memory cells and the power management circuits produce Vbb pump signals once before and once after the internal refresh pulse.
Claim 31
Dependent Claim
53 words
The dynamic random access memory part of claim 17, wherein the power management circuits cause production of an internal refresh pulse for refreshing the row of memory cells and the power management circuits operating the first circuits selectably before and selectably after the internal refresh pulse to refresh of a group of cells.
Claim 32
Dependent Claim
55 words
The dynamic random access memory part of claim 17, wherein the second circuits are connected between Vdd and Vss supply leads and the power management circuits include a switch circuit for each of the second circuits that switches the Vdd connection to another Vss supply lead to remove power from each of the second circuits.
Claim 33
Dependent Claim
170 words
A process of maintaining data in a personal computer, the process comprising: receiving a user indication of a sleep mode; retaining data in dynamic random access memory pans in the personal computer during the sleep mode; producing signals to the dynamic random access memory parts indicating the sleep mode is to be effected; effecting, in response to the producing signals to the dynamic random access memory parts indicating the sleep mode is to be effected, self-refresh of dynamic memory cells in the dynamic random access memory pans, the effecting including reducing the self-refresh rate from a normal refresh rate and operating first circuits that are required to operate to effect the self-refresh substantially only at refresh of a row of memory cells; and removing, in response to the producing signals to the dynamic random access memory parts indicating the sleep mode is to be effected, electrical power that is normally applied to second circuits included in the dynamic random access memory parts that can have power removed during the self-refresh.
Claim 34
Dependent Claim
170 words
A process of maintaining data in a personal computer, the process comprising: receiving a user indication of a sleep mode; retaining data in dynamic random access memory pans in the personal computer during the sleep mode; producing signals to the dynamic random access memory parts indicating the sleep mode is to be effected; effecting, in response to the producing signals to the dynamic random access memory parts indicating the sleep mode is to be effected, self-refresh of dynamic memory cells in the dynamic random access memory pans, the effecting including reducing the self-refresh rate from a normal refresh rate and operating first circuits that are required to operate to effect the self-refresh substantially only at refresh of a row of memory cells; and removing, in response to the producing signals to the dynamic random access memory parts indicating the sleep mode is to be effected, electrical power that is normally applied to second circuits included in the dynamic random access memory parts that can have power removed during the self-refresh.
Claim 35
Dependent Claim
22 words
The process of claim 31, wherein the reducing the self-refresh rate includes reducing the frequency of an oscillator in the memory part.
Claim 36
Dependent Claim
31 words
The process of claim 31, wherein the operating first circuits includes operating a Vbb pump once before and once after, but not during, the refresh of a row of memory cells.
Claim 37
Dependent Claim
18 words
The process of claim 31, wherein the removing electrical power includes removing electrical power from the column paths.
Claim 38
Dependent Claim
25 words
The process of claim 31, wherein the producing signals includes producing CBR refresh signals with the row address strobe inactive for at least ten microseconds.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-11-14 | 1998-05-16 | 1998-11-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-11-14 | 2002-05-16 | 2002-11-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-11-14 | 2006-05-16 | 2006-11-15 | $7700.00 | Window Closed / Lapsed |