Patent US5495437A successfully refreshed from Google Patents.
US5495437A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Non-volatile RAM transferring data between ferro-electric capacitors and a memory cell
Assignee: Progressive Semiconductor Solutions LLC
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Filing: 1994-07-05
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Granted: 1996-02-27
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Expires: 2014-07-05
Abstract
Abstract A non-volatile RAM circuit (10) uses ferro-electric capacitors (14, 16) to store data in a dormant state. Data is initially stored on the ferro-electric capacitors. The data stored on the ferro-electric capacitors is transferred to a memory cell (25) when the RAM circuit is powered up. Subsequent read operations after the power-up sequence obtain data from the memory cell instead of the ferro-electric capacitors. Any write operation during the power-up sequence is stored in the memory cell. When power is removed, the ferro-electric capacitors are updated with the present state of the memory cell. The endurance and data retention time of the ferro-electic capacitors increases by accessing data from the memory cell.
Inventors
- 👤 Jy-Der D. Tai
- 👤 Andreas A. Wild
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:32
CPC Classifications
G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
339 words
A ferro-electric RAM circuit, comprising: a memory cell having first and second data bitlines; a first capacitor coupled between said first data bitline and a first power supply conductor; a second capacitor coupled between said second data bitline and said first power supply conductor; first means for coupling first and second complementary data signals to said first and second data bitlines respectively in response to a passgate control signal; third and fourth capacitors each having first and second terminals, said first terminals receiving a driveline control signal; and second means for coupling said second terminals of said third and fourth capacitors to said first and second data bitlines respectively in response to a wordline control signal; where said memory cell includes, (a) a first transistor having a gate, a drain and a source, said gate being coupled to said second data bitline, said drain being coupled to said first data bitline, (b) a second transistor having a gate, a drain and a source, said drain being coupled to said first data bitline, said gate being coupled to said second data bitline, said source being coupled to said first power supply conductor, (c) a third transistor having a gate, a drain and a source, said gate being coupled to said first data bitline, said drain being coupled to said second data bitline, (d) a fourth transistor having a gate, a drain and a source, said drain being coupled to said second data bitline, said gate being coupled to said first data bitline, said source being coupled to said first power supply conductor, and (e) a fifth transistor having a gate, a drain and a source, said source being coupled to a second power supply conductor, said gate being coupled for receiving an enable control signal, said drain being coupled to said sources of said first and third transistors for isolating said sources of said first and third transistors from said second power supply conductor and allowing a maximum difference voltage to develop between said first and second data bit lines.
Claim 2
Dependent Claim
339 words
A ferro-electric RAM circuit, comprising: a memory cell having first and second data bitlines; a first capacitor coupled between said first data bitline and a first power supply conductor; a second capacitor coupled between said second data bitline and said first power supply conductor; first means for coupling first and second complementary data signals to said first and second data bitlines respectively in response to a passgate control signal; third and fourth capacitors each having first and second terminals, said first terminals receiving a driveline control signal; and second means for coupling said second terminals of said third and fourth capacitors to said first and second data bitlines respectively in response to a wordline control signal; where said memory cell includes, (a) a first transistor having a gate, a drain and a source, said gate being coupled to said second data bitline, said drain being coupled to said first data bitline, (b) a second transistor having a gate, a drain and a source, said drain being coupled to said first data bitline, said gate being coupled to said second data bitline, said source being coupled to said first power supply conductor, (c) a third transistor having a gate, a drain and a source, said gate being coupled to said first data bitline, said drain being coupled to said second data bitline, (d) a fourth transistor having a gate, a drain and a source, said drain being coupled to said second data bitline, said gate being coupled to said first data bitline, said source being coupled to said first power supply conductor, and (e) a fifth transistor having a gate, a drain and a source, said source being coupled to a second power supply conductor, said gate being coupled for receiving an enable control signal, said drain being coupled to said sources of said first and third transistors for isolating said sources of said first and third transistors from said second power supply conductor and allowing a maximum difference voltage to develop between said first and second data bit lines.
Claim 3
Dependent Claim
19 words
The ferro-electric RAM circuit of claim 1 wherein said third and fourth capacitors are made of a ferro-electric material.
Claim 4
Dependent Claim
53 words
The ferro-electric RAM circuit of claim 2 wherein said first means includes a sixth transistor having a gate, a drain and a source, said drain being coupled to said first data bitline, said gate being coupled for receiving said passgate control signal, said source being coupled for receiving said first complementary data signal.
Claim 5
Dependent Claim
54 words
The ferro-electric RAM circuit of claim 3 wherein said first means further includes a seventh transistor having a gate, a drain and a source, said drain being coupled to said second data bitline, said gate being coupled for receiving said passgate control signal, said source being coupled for receiving said second complementary data signal.
Claim 6
Dependent Claim
54 words
The ferro-electric RAM circuit of claim 4 wherein said second means includes an eighth transistor having a gate, a drain and a source, said drain being coupled to said first data bitline, said gate being coupled for receiving said wordline control signal, said source being coupled to said second terminal of said third capacitor.
Claim 7
Dependent Claim
55 words
The ferro-electric RAM circuit of claim 5 wherein said second means further includes a ninth transistor having a gate, a drain and a source, said drain being coupled to said second data bitline, said gate being coupled for receiving said wordline control signal, said source being coupled to said second terminal of said fourth capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |