Ferroelectric programming cell for configurable logic

Claim 2

A ferroelectric programming cell, the cell comprising: (a) a volatile memory cell having a positive power input and a negative power input and first and second internal nodes which are latched in complementary states when the positive power input is held to a maximum allowed voltage level and the negative power input is held at ground, and are not latched when the positive power input is held at ground and the negative power input is held at the maximum allowed voltage level; (b) a node enabling switching means connected to the volatile memory cell for enabling an external signal generator to set the values of the first and second internal nodes; (c) a configuration cell having two data terminals and first and second complementary control inputs respectively connected to the first and second internal nodes for causing the two data terminals to be connected when the control inputs are set in one state and the data terminals to be isolated when the control inputs are set to the opposite state; (d) first and second substantially identical capacitance-dividers, each including a first ferroelectric capacitance means for storing a non-volatile configuration state, with a driving terminal connected to the external signal generator and a measurement terminal connected to a second capacitance means that enables the volatile memory cell to measure the non-volatile configuration state of the first ferroelectric capacitance means, and a measurement clearing switching means for enabling the external signal generator to force the voltage at the measurement terminal to ground and connected to the first ferroelectric capacitance measurement terminal and to ground; (e) first and second substantially identical loading switching means for enabling the connected external signal generator to transfer the non-volatile configuration state stored in the first and second capacitance dividers to the volatile memory cell, each loading switching means connecting the measurement terminal within a corresponding capacitance divider to one of the complementary internal nodes of the volatile memory cell; each internal node of the volatile memory cell being connected respectively to one of the complementary control inputs of the configuration cell.

Claim 3

A ferroelectric programming cell as in claim 1 wherein all the switching means are matched CMOS transistors.

Claim 4

The ferroelectric programming cell as in claim 1 wherein the second capacitance means comprises a ferroelectric capacitor.

Claim 5

A ferroelectric programming cell, said cell comprising: (a) a volatile memory cell having a positive power input and a negative power input and first and second internal nodes which are latched in complementary states when the positive power input is held to a maximum allowed voltage level and the negative power input is held at ground, and are not latched when the positive power input is held at ground and the negative power input is held at the maximum allowed voltage level; (b) node enabling switching means connected to the volatile memory cell for enabling an external signal generator to set the values of the first and second internal nodes; (c) a configuration cell having two data terminals and first and second complementary control inputs respectively connected to the first and second internal nodes, said configuration cell causing the two data terminals to be connected when the control inputs are set in one state and the data inputs to be isolated when each control inputs are set to the opposite state; (d) first and second capacitance-dividers each including a first ferroelectric capacitance means for storing a non-volatile configuration state using a storing a non-volatile configuration state using a ferroelectric capacitor, and having a driving terminal and a measurement terminal, the driving terminal connected to the external signal generator and the measurement terminal connected to a second capacitance means for enabling the volatile memory cell to measure the non-volatile configuration state of the first ferroelectric capacitance means connected to the first ferroelectric capacitance means measurement terminal, and a measurement clearing switching means for enabling the external signal generator to force the voltage at the measurement terminal to ground and connected to the first ferroelectric capacitance measurement terminal and to, ground and wherein the capacitance of the first capacitance-divider's first ferroelectric capacitance means in the "up" polarization is a first value C1up1 and is a second value C1down1 in the "down" polarization, and where in the capacitance of the second capacitance-divider's first ferroelectric capacitance means in the "up" polarization is a third value C2up1 and is a fourth value C2down1 in the "down" polarization and wherein the capacitance of the first capacitance divider's second capacitance means is a fifth value C1 and the capacitance of the second capacitance divider's second capacitance means is a sixth value C2, and wherein C1up1*C2> C2down1*C1 and wherein C1down*C2>C2up1*C1; and (e) two substantially identical loading switching means for enabling the connected external signal generator to transfer the nonvolatile configuration state stored in the capacitance dividers to the volatile memory cell, connecting the measurement terminal within a capacitance divider to one of the complementary internal nodes of the volatile memory cell; each internal node of the volatile memory cell being connected respectively to one of the complementary control inputs of the configuration cell.

Claim 6

A ferroelectric programming cell, said cell comprising: (a) a volatile memory cell having a positive power input and a negative power input and first and second internal nodes which are latched in complementary states when the positive power input is held to a maximum allowed voltage level and the negative power input is held at ground, and are not latched when the positive power input is held at ground and the negative power input is held at the maximum allowed voltage level; (b) node enabling switching means connected to the volatile memory cell for enabling an external signal generator to set the values of the first and second internal nodes; (c) a configuration cell having two data terminals and first and second complementary control inputs respectively connected to the first and second internal nodes, said configuration cell causing the two data terminals to be connected when the control inputs are set in one state and the data inputs to be isolated when each control inputs are set to the opposite state; (d) first and second capacitance-dividers each including a first ferroelectric capacitance means for storing a non-volatile configuration state using a storing a non-volatile configuration state using a ferroelectric capacitor, and having a driving terminal and a measurement terminal, the driving terminal connected to the external signal generator and the measurement terminal connected to a second capacitance means for enabling the volatile memory cell to measure the non-volatile configuration state of the first ferroelectric capacitance means connected to the first ferroelectric capacitance means measurement terminal, and a measurement clearing switching means for enabling the external signal generator to force the voltage at the measurement terminal to ground and connected to the first ferroelectric capacitance measurement terminal and to, ground and wherein the capacitance of the first capacitance-divider's first ferroelectric capacitance means in the "up" polarization is a first value C1up1 and is a second value C1down1 in the "down" polarization, and where in the capacitance of the second capacitance-divider's first ferroelectric capacitance means in the "up" polarization is a third value C2up1 and is a fourth value C2down1 in the "down" polarization and wherein the capacitance of the first capacitance divider's second capacitance means is a fifth value C1 and the capacitance of the second capacitance divider's second capacitance means is a sixth value C2, and wherein C1up1*C2> C2down1*C1 and wherein C1down*C2>C2up1*C1; and (e) two substantially identical loading switching means for enabling the connected external signal generator to transfer the nonvolatile configuration state stored in the capacitance dividers to the volatile memory cell, connecting the measurement terminal within a capacitance divider to one of the complementary internal nodes of the volatile memory cell; each internal node of the volatile memory cell being connected respectively to one of the complementary control inputs of the configuration cell.