US5495192A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sample hold circuit
Assignee: Yozan Inc
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Filing: 1995-06-07
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Granted: 1996-02-27
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Expires: 2015-06-07
Abstract
Abstract A sample and hold circuit to reduce hold error when analog data is held and transferred. The circuit includes a plurality of capacitors and inverters for guaranteeing level, selectively holds an input voltage at one capacitor by a first switching means, transfers charged voltage to a second capacitance by a second switching means and reduces data transfer time.
Inventors
- 👤 Guoliang Shou
- 👤 Weikang Yang
- 👤 Sunao Takatori
- 👤 Makoto Yamamoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 13:51
CPC Classifications
G; G11; G11C; G11C27/00; G11C27/02; G11C27/024; G11C27/026
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
372 words
A sample and hold circuit comprising: a first sample and hold circuit for receiving an input voltage, said first sample and hold circuit comprising: a plurality of sampling circuits, each of said sampling circuits including a first switch for selectively supplying said input voltage to a corresponding one of said sampling circuits, a first inverter having an input and an output, a first capacitance connected between said input of said first inverter and said first switch, a first feedback capacitance connecting said output of said first inverter to said input of said first inverter, and a second switch, for selectively connecting said output of said first inverter to an output node, said output node connecting outputs from all sample circuits, and an output circuit including a second inverter having an input and an output, an output capacitance connected between said output node and said second inverter input, and a second feedback capacitance connecting said output of said second inverter to said input of said second inverter; a plurality of second sample and hold circuits connected in series, a first one of said second sample and hold circuits being connected in parallel with said first sample and hold circuit to said input voltage, each second sample and hold circuit comprising a third switch, a third capacitance, a third inverter, a fourth switch, a fourth capacitance and a fourth inverter connected in series, each second sample and hold circuit further comprising a third feedback capacitance for connecting an output to an input of said third inverter and a fourth feedback capacitance for connecting an output to an input of said third inverter; and a plurality of third sample and hold circuits connected in series, a first one of said third sample and hold circuits being connected to an output of said first sample and hold circuit, each third sample and hold circuit comprising a fifth switch, a fifth capacitance, a fifth inverter, a sixth switch, a sixth capacitance and a sixth inverter connected in series, each third sample and hold circuit further comprising a fifth feedback capacitance for connecting said output to said input of said fifth inverter and a sixth feedback capacitance for connecting said output to said input of said sixth inverter.
Claim 2
Dependent Claim
372 words
A sample and hold circuit comprising: a first sample and hold circuit for receiving an input voltage, said first sample and hold circuit comprising: a plurality of sampling circuits, each of said sampling circuits including a first switch for selectively supplying said input voltage to a corresponding one of said sampling circuits, a first inverter having an input and an output, a first capacitance connected between said input of said first inverter and said first switch, a first feedback capacitance connecting said output of said first inverter to said input of said first inverter, and a second switch, for selectively connecting said output of said first inverter to an output node, said output node connecting outputs from all sample circuits, and an output circuit including a second inverter having an input and an output, an output capacitance connected between said output node and said second inverter input, and a second feedback capacitance connecting said output of said second inverter to said input of said second inverter; a plurality of second sample and hold circuits connected in series, a first one of said second sample and hold circuits being connected in parallel with said first sample and hold circuit to said input voltage, each second sample and hold circuit comprising a third switch, a third capacitance, a third inverter, a fourth switch, a fourth capacitance and a fourth inverter connected in series, each second sample and hold circuit further comprising a third feedback capacitance for connecting an output to an input of said third inverter and a fourth feedback capacitance for connecting an output to an input of said third inverter; and a plurality of third sample and hold circuits connected in series, a first one of said third sample and hold circuits being connected to an output of said first sample and hold circuit, each third sample and hold circuit comprising a fifth switch, a fifth capacitance, a fifth inverter, a sixth switch, a sixth capacitance and a sixth inverter connected in series, each third sample and hold circuit further comprising a fifth feedback capacitance for connecting said output to said input of said fifth inverter and a sixth feedback capacitance for connecting said output to said input of said sixth inverter.
Claim 3
Dependent Claim
51 words
The sample and hold circuit of claim 1, further comprising a plurality of first grounding capacitances, each of said first grounding capacitances being connected between an input terminal of one of said third capacitances and ground, and between an input terminal of one of said fifth capacitances and said ground, respectively.
Claim 4
Dependent Claim
46 words
The sample and hold circuit of claim 2, further comprising a plurality of second grounding capacitances, each connected between an input terminal of one of said fourth capacitances and said ground, and between an input terminal of one of said sixth capacitance and said ground, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |