Method and apparatus for an improved multiple channel sensor interface circuit

Claim 2

A multiple channel sensor interface circuit comprising: a plurality of input integrator circuits each having an input coupled to one fo plurality of input signals, and each having an output; a switched capacitor multiplexer having a plurality of inputs each coupled to a respective output of one of said input integrator circuits, operable to receive input data from each of said input integrator circuits in parallel, further operable to store said input data on capacitive storage elements, and operable to provide each one of said input data signals at an output thereof for transmission in a sequential fashion in response to one or more control signals; an output integrator stage coupled to said switched capacitor multiplexer; and an output sample-hold circuit coupled to said output integrator stage.

Claim 3

The multiple channel sensor interface circuit of claim 1, wherein said input integrator circuits comprise an analog amplifier having a capacitive storage element connected in a feedback configuration.

Claim 4

The multiple channel sensor interface circuit of claim 1, wherein said switched capacitor multiplexer comprises a plurality of capacitive storage elements coupled in parallel and operable to receive input samples in parallel and transmit said input samples sequentially, respective to timing circuitry.

Claim 5

The switched capacitor multiplexer of claim 3 wherein each of said capacitive storage elements comprises a capacitor coupled to a pair of switches operable to enable the capacitor to receive sensor input from the respective input integrator circuit and further coupled to a pair of switches operable to enable said capacitive storage element to sequentially transmit and sensor input.

Claim 6

The multiple channel sensor interface circuit of claim 1 wherein said output integrator stage comprises an analog amplifier having a capacitive storage element in a feedback amplifier configuration.

Claim 7

The multiple channel sensor interface circuit of claim 1 and further comprising timing circuit coupled to said switched capacitor multiplexer for supplying said control signals.

Claim 8

The multiple channel sensor interface circuit of claim 6 wherein said timing circuitry further comprises logic circuitry operable to enable said switched capacitor multiplexer to receive sensor inputs concurrently and transmit said sensor inputs sequentially.

Claim 9

The multiple channel sensor interface circuit of claim 1 wherein said switched capacitor multiplexer further comprises two reference voltages operable for setting the output voltage level by charging the capacitive storage elements of said switched capacitor multiplexer relative to one of said reference voltages and discharging said capacitive storage elements relative to the second of said reference voltages.

Claim 10

A multiple channel sensor interface circuit; comprising: a plurality of input integrator circuits each having an input coupled to one of a plurality of input signals, and each having an output; a switched capacitor multiplexer having a plurality of inputs each coupled to a respective output of one of said input integrator circuits, operable to receive input data from each of said input integrator circuits in parallel, further operable to store said input data on capacitive storage elements, and operable to provide each one of said input data signals at an output thereof for transmission in a sequential fashion in response to one or more control signals; an output integrator stage coupled to said switched capacitor multiplexer; and an analog-to-digital converter circuit coupled to said output integrator stage.

Claim 11

A multiple channel sensor interface circuit; comprising: a plurality of input integrator circuits each having an input coupled to one of a plurality of input signals, and each having an output; a switched capacitor multiplexer having a plurality of inputs each coupled to a respective output of one of said input integrator circuits, operable to receive input data from each of said input integrator circuits in parallel, further operable to store said input data on capacitive storage elements, and operable to provide each one of said input data signals at an output thereof for transmission in a sequential fashion in response to one or more control signals; an output integrator stage coupled to said switched capacitor multiplexer; and an analog-to-digital converter circuit coupled to said output integrator stage.

Claim 12

An integrated circuit implementing a multiple channel sensor interface, comprising: a plurality of inputs; a plurality of input integrator circuits each coupled to one of said inputs; a switched capacitor multiplexer having a plurality of inputs each coupled to one of said input integrator circuits, having a plurality of capacitive storage elements each selectively coupled to one of said input integrator circuits by first switches, each selectively coupled to a reference voltage by second switches, operable for storing the data from each of said inputs by use of said first and second of switches operable for charging each of said capacitive storage elements with the respective data from the respective input integrator circuit, and having a single output operable for sequentially transmitting each of said stored data from said inputs by sequentially discharging each of said capacitive storage elements relative to said reference voltage through the use of said first and second switches associated with each of said capacitive storage elements in response to one or more control signals; an output integrator stage coupled to said switched capacitor multiplexer; and an output analog-to-digital converter stage coupled to said output integrator stage and further coupled to an output node.

Claim 13

An integrated circuit implementing a multiple channel sensor interface, comprising: a plurality of inputs; a plurality of input integrator circuits each coupled to one of said inputs; a switched capacitor multiplexer having a plurality of inputs each coupled to one of said input integrator circuits, having a plurality of capacitive storage elements each selectively coupled to one of said input integrator circuits by first switches, each selectively coupled to a reference voltage by second switches, operable for storing the data from each of said inputs by use of said first and second of switches operable for charging each of said capacitive storage elements with the respective data from the respective input integrator circuit, and having a single output operable for sequentially transmitting each of said stored data from said inputs by sequentially discharging each of said capacitive storage elements relative to said reference voltage through the use of said first and second switches associated with each of said capacitive storage elements in response to one or more control signals; an output integrator stage coupled to said switched capacitor multiplexer; and an output analog-to-digital converter stage coupled to said output integrator stage and further coupled to an output node.

Claim 14

The integrated circuit of claim 10, wherein each of said input integrator circuits comprise an analog amplifier having a capacitive storage element connected in a feedback configuration.

Claim 15

The integrated circuit of claim 10, wherein said plurality of capacitive storage elements are arranged in parallel and operable to receive the output of respective input integrator circuits in parallel and further operable to transmit said input samples sequentially, responsive to timing circuitry.

Claim 16

The integrated circuit of claim 10 wherein said output integrator stage comprises an analog amplifier having a capacitor storage element coupled in a feedback amplifier configuration.

Claim 17

The integrated circuit of claim 10 and further comprising timing circuitry coupled to said input integrator circuits, further coupled to said switched capacitor multiplexer, and further coupled to said output amplifier, for enabling the sampling of the inputs in parallel and the transmission of the sensed data in a predetermined sequence.

Claim 20

The method of claim 15, wherein the step of providing said input integrator circuits comprises providing a plurality of analog amplifiers each having a capacitive storage element connected in a feedback configuration.

Claim 21

The method of claim 15, wherein said step of coupling said input integrator circuits to a switched capacitor multiplexer comprises coupling said input integrator circuits to a switched capacitor multiplexer having two reference voltages, one for charging and another for discharging the switched capacitor multiplexer, and operable to set the output voltage level by charging the capacitors relative to the first of said reference voltages and discharging the capacitors relative to the second of said reference voltages so that the voltage at the output of the switched capacitor multiplexer is a desired voltage relative to the voltage at the input of the switched capacitor multiplexer.