Differential switched capacitor integrator using a single integration capacitor

Claim 1

A differential switched capacitor integrator, operable for sampling analog differential signals coupled to two differential input terminals and for providing corresponding selectively filtered differential output signals at two differential output terminals, comprising: two paths relative to said two differential input and output terminals at a floating potential with respect to a common ground terminal, said two paths being substantially identical and each path including: (a) a first switch connected between a corresponding one of said input terminals and a first plate of a sampling capacitor; (b) a second switch connected between said first plate and ground; (c) a third switch connected between a second plate of said sampling capacitor and a corresponding one of said output terminals; (d) a fourth switch connected between the second plate of said sampling capacitor and to a corresponding one of two plates of a floating integration capacitor; two unity gain buffers, each respectively integrated in one of said two paths, each of said buffers having a non-inverting and an inverting input terminal and an output terminal constituting one of said two differential output terminals of the integrator, the output terminal of each unity gain buffer being short-circuited to its corresponding inverting input terminal, the non-inverting terminal of each unity gain buffer being connected to a corresponding one of the two plates of said floating integration capacitor; and first and second non-overlapping clock signals being applied, respectively, to said first and third switches and to said second and fourth switches.