Patent JPH0331333A successfully refreshed from Google Patents.
US4714843A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor chip power supply monitor circuit arrangement
Assignee: STMicroelectronics lnc USA
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Filing: 1985-08-30
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Granted: 1987-12-22
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Expires: 2005-08-30
Abstract
Abstract A circuit arrangement (13) for monitoring power supplies in N-channel CMOS devices, comprising elements for sampling of a bandgap voltage reference quantity (41), comparing the reference quantity to a monitored power supply voltage level (38), and compensating (49) for the offset voltage produced in the comparator element (31) conducting the comparison.
Inventors
- 👤 Michael D. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 15:30
CPC Classifications
G; G01; G01R; G01R19/00; G01R19/165; G01R19/16533; G01R19/16538; G01R19/16542; G01R31/00; G01R31/36
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
328 words
A circuit arrangement for monitoring the power supply of N-well CMOS device comprising an amplifier (31) having two inputs including an inverting input, a non-inverting input and a single output, and adapted to be switched between modes including a comparator mode and an amplifying mode, an output terminal, an input terminal to which is applied the supply voltage being monitored, a first switch means, serially connected between the output of the amplifying means and the output terminal, which when closed connects the output of the amplifying means to the output terminal, a second switch means, connected between the input terminal and one of the two inputs of the amplifying means, which when closed provides a sample of the supply voltage on said one input of the amplifying means, a ground terminal, a third switch means, connected between the ground terminal and said one input of the amplifying means, which is operated out of phase with said second switch, a first capacitor means having first and second terminals across which is periodically stored a reference voltage for comparison with the supply voltage, means for periodically storing the reference voltage on said first capacitor means, fourth, fifth, sixth, and seventh switch means, an input capacitor means including first and second terminals of which said first terminal is connected to the other of the two inputs of the amplifier means, and of which said second terminal is connected to the first terminal of the first capacitor by way of said fifth switch and to the second terminal of the first capacitor means by way of the sixth switch means, said second terminal of the first capacitor means also being connected to the ground terminal by way of the seventh switch means, the fourth switch means being connected between the output of the amplifier means and said other input of the amplifier, and means for periodically connecting said one terminal of the input capacitor means to the output of the amplifier means.
Claim 2
Dependent Claim
328 words
A circuit arrangement for monitoring the power supply of N-well CMOS device comprising an amplifier (31) having two inputs including an inverting input, a non-inverting input and a single output, and adapted to be switched between modes including a comparator mode and an amplifying mode, an output terminal, an input terminal to which is applied the supply voltage being monitored, a first switch means, serially connected between the output of the amplifying means and the output terminal, which when closed connects the output of the amplifying means to the output terminal, a second switch means, connected between the input terminal and one of the two inputs of the amplifying means, which when closed provides a sample of the supply voltage on said one input of the amplifying means, a ground terminal, a third switch means, connected between the ground terminal and said one input of the amplifying means, which is operated out of phase with said second switch, a first capacitor means having first and second terminals across which is periodically stored a reference voltage for comparison with the supply voltage, means for periodically storing the reference voltage on said first capacitor means, fourth, fifth, sixth, and seventh switch means, an input capacitor means including first and second terminals of which said first terminal is connected to the other of the two inputs of the amplifier means, and of which said second terminal is connected to the first terminal of the first capacitor by way of said fifth switch and to the second terminal of the first capacitor means by way of the sixth switch means, said second terminal of the first capacitor means also being connected to the ground terminal by way of the seventh switch means, the fourth switch means being connected between the output of the amplifier means and said other input of the amplifier, and means for periodically connecting said one terminal of the input capacitor means to the output of the amplifier means.
Claim 3
Dependent Claim
37 words
The circuit arrangement of claim 1 in which the sample of the supply voltage is applied to the non-inverting input of the amplifier and the reference voltage and an offset voltage are applied to the inverting input.
Claim 4
Dependent Claim
127 words
The circuit arrangement of claim 1 in further combination with means for setting the switches whereby three operating modes of the amplifier means are realized of which during the comparator mode the non-inverting input is connected to the input terminal for applying the supply voltage thereto and the inverting input has applied thereto the voltage across the input capacitor; during a zero offset mode, the non-inverting terminal is connected to ground, the inverting terminal is connected to the output, and the second terminal of the input capacitor is connected to ground whereby a zero offset voltage is stored on the input capacitor, and during the amplifying mode the reference voltage is established across the second capacitor and combined with the zero offset voltage on the input capacitor.
Claim 5
Dependent Claim
82 words
The circuit arrangement of claim 1 in further combination with means for setting the switches such that during a first mode the first, second, fifth and seventh switches are closed and the third, fourth and sixth switches open, during a second mode, the first and second are open, and the third, fourth, fifth, sixth and seventh are closed, and a third mode during which the first, second, fourth, fifth and seventh switches are open and the third and sixth switches are closed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-12-21 | 1991-06-22 | 1991-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-12-21 | 1995-06-22 | 1995-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-12-21 | 1999-06-22 | 1999-12-22 | $7700.00 | Window Closed / Lapsed |