Sample-and-hold circuit

Abstract

Abstract PURPOSE:To suppress the effect of output ripple of a frequency voltage converter by producing a sampling pulse while using an input FM signal as a reference at each repetitive period of transmission start. CONSTITUTION:Monostable multivibrators 5, 6 are operated sequentially by a transmission trigger pulse and its Q output is fed to a DFF8. On the other hand, an input FM signal is given to a monostable multivibrator 7, its Q output is given to an AND gate 9 and a Q' output is given to an FF8 as a clock. A sampling pulse is produced by AND between the Q output of the FF8 and the Q output of the monostable multivibrator 7. Moreover, an input FM signal is fed to a sample-and-hold circuit 10 via a frequency voltage converter 4 and sampled and held by a sampling pulse from the gate 9. As a result, a value of a prescribed position of a ripple waveform of the input signal is sampled and the effect of ripple is reduced.

Inventors

• 👤 Takashi Konagai
• 👤 小長井　孝
• 👤 Norio Isobe
• 👤 磯部　憲雄

Bibliographic Details