US5495188A
Expired / Lapsed
US
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Pulsed static CMOS circuit
Assignee: International Business Machines Corp
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Filing: 1995-04-13
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Granted: 1996-02-27
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Expires: 2015-04-13
Abstract
Abstract A pulsed static CMOS circuit. Improved static CMOS circuit speed is achieved without using a clock scheme like that in dynamic CMOS circuits. The disclosed circuit family is a pulsed static CMOS circuit which makes only a single transition during evaluation. The circuit is reset to a predetermined state by an input pattern, which is in favor of the faster switching direction of the static CMOS.
Inventors
- 👤 Chih-Liang Chen
- 👤 Gary S. Ditlow
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:26
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01728; H03K19/01742
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
93 words
An electrical logic circuit, comprising: a first dynamic latch having a data input and a system clock input, the dynamic latch producing a pulsed output characterized by an evaluate edge and a data reset edge; a logic circuit coupled to receive the pulsed output of the first dynamic latch, the logic circuit comprising means for producing a pulsed output signal, one edge of which comprises evaluate information, the logic circuit being characterized in that it has no clock input; a second dynamic latch coupled to receive the pulsed output from the logic circuit.
Claim 2
Dependent Claim
93 words
An electrical logic circuit, comprising: a first dynamic latch having a data input and a system clock input, the dynamic latch producing a pulsed output characterized by an evaluate edge and a data reset edge; a logic circuit coupled to receive the pulsed output of the first dynamic latch, the logic circuit comprising means for producing a pulsed output signal, one edge of which comprises evaluate information, the logic circuit being characterized in that it has no clock input; a second dynamic latch coupled to receive the pulsed output from the logic circuit.
Claim 3
Dependent Claim
83 words
The circuit of claim 1, wherein the logic circuit comprises a plurality of stages of logic gates, the gates in a first stage of the plurality of stages being coupled to receive the pulsed output of the first latch, the reset edge of the pulsed output of the first latch having a first reset characteristic, and the first stage of logic circuits comprising means for producing a pulsed output signal having an evaluate edge and a reset edge having a second reset characteristic.
Claim 4
Dependent Claim
19 words
The circuit of claim 2, wherein the first reset characteristic is reset-high, and the second reset characteristic is reset-low.
Claim 5
Dependent Claim
57 words
The circuit of claim 2, wherein a second stage of the plurality of stages is coupled to receive the pulsed output from the first stage and produce a pulsed output having an evaluate edge and a reset edge, the reset edge having a reset characteristic opposite the reset characteristic of reset edge output from the first stage.
Claim 6
Dependent Claim
14 words
The circuit of claim 4, wherein the first stage comprises a static NAND gate.
Claim 7
Dependent Claim
14 words
The circuit of claim 4, wherein the second stage comprises a static NOR gate.
Claim 8
Dependent Claim
46 words
The circuit of claim 1, wherein the first dynamic latch comprises: a static latch having means for receiving the data input and producing a data output signal; and a pulse generator coupled to receive the data output signal and including means for producing the pulsed output.
Claim 9
Dependent Claim
13 words
The circuit of claim 7, wherein the pulse generator is a tri-state inverter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-26 | 1999-08-28 | 2000-02-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-26 | 2003-08-28 | 2004-02-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-26 | 2007-08-28 | 2008-02-27 | $7700.00 | Window Closed / Lapsed |