Enhancement in throughput and planarity during CMP using a dielectric stack containing HDP-SiO2 films

Claim 1

A method of constructing a planarized interconnection layer on a semiconductor substrate having both high and low aspect ratio conductors, said method comprising: (a) providing a layer of patterned conductors formed on said substrate, said patterned conductors deposited to a first thickness above said substrate; (b) depositing a conformal dielectric seed layer over said conductors and said substrate; (c) depositing a dielectric gap-fill layer over said dielectric seed layer by simultaneous CVD and dc-bias sputtering, using a gas mixture comprised of silicon-containing, oxygen-containing, and inert components, said gap-fill layer having a second thickness, as measured in one or more gaps between said conductors, greater than or approximately equal to said first thickness, thereby planarizing said interconnection layer at said high aspect ratio conductors; (d) depositing a conformal dielectric polish layer over said gap-fill layer, said polish layer comprised of materials selected from the group consisting of: PETEOS, BPSG, BSG, PSG, silane oxide, and combinations thereof, and (e) planarizing said interconnection layer at said low aspect ratio conductors by a chemical-mechanical polishing process to provide a top dielectric surface which is at least 50% of said first thickness above the tops of said conductors, whereby decreased deposition thickness and decreased polish time are required to obtain a desired final dielectric thickness and planarity.

Claim 2

A method of constructing a planarized interconnection layer on a semiconductor substrate having both high and low aspect ratio conductors, said method comprising: (a) providing a layer of patterned conductors formed on said substrate, said patterned conductors deposited to a first thickness above said substrate; (b) depositing a conformal dielectric seed layer over said conductors and said substrate; (c) depositing a dielectric gap-fill layer over said dielectric seed layer by simultaneous CVD and dc-bias sputtering, using a gas mixture comprised of silicon-containing, oxygen-containing, and inert components, said gap-fill layer having a second thickness, as measured in one or more gaps between said conductors, greater than or approximately equal to said first thickness, thereby planarizing said interconnection layer at said high aspect ratio conductors; (d) depositing a conformal dielectric polish layer over said gap-fill layer, said polish layer comprised of materials selected from the group consisting of: PETEOS, BPSG, BSG, PSG, silane oxide, and combinations thereof, and (e) planarizing said interconnection layer at said low aspect ratio conductors by a chemical-mechanical polishing process to provide a top dielectric surface which is at least 50% of said first thickness above the tops of said conductors, whereby decreased deposition thickness and decreased polish time are required to obtain a desired final dielectric thickness and planarity.

Claim 8

A method of constructing a planarized interconnection layer on a semiconductor substrate having both high and low aspect ratio conductors, said method comprising: (a) providing a layer of patterned conductors formed on said substrate, said patterned conductors having tops which are a first thickness above said substrate; (b) depositing a conformal dielectric seed layer over said conductors and said substrate, in a deposition chamber; (c) depositing, also in said deposition chamber, a dielectric gap-fill layer over said seed layer by a method of simultaneous CVD and de-bias sputtering, using a gas mixture comprised of silane, oxygen-containing, and group VIH gas components, said gap-fill layer having a second thickness, as measured in one or more gaps between said conductors, greater than or approximately equal to said first thickness, thereby planarizing said interconnection layer over said high aspect ratio conductors; and (d) planarizing said interconnection layer over said low aspect ratio conductors by a chemical-mechanical polishing process to provide a top dielectric surface which is at least 50% of said first thickness above the tops of said conductors, whereby said seed layer is used to prevent said dc-bias sputtering from sputtering material from said conductors, and whereby decreased deposition thickness and decreased polish time are required to obtain a desired final dielectric thickness and planarity.

Claim 9

A method of constructing a planarized interconnection layer on a semiconductor substrate having both high and low aspect ratio conductors, said method comprising: (a) providing a layer of patterned conductors formed on said substrate, said patterned conductors having tops which are a first thickness above said substrate; (b) depositing a conformal dielectric seed layer over said conductors and said substrate, in a deposition chamber; (c) depositing, also in said deposition chamber, a dielectric gap-fill layer over said seed layer by a method of simultaneous CVD and de-bias sputtering, using a gas mixture comprised of silane, oxygen-containing, and group VIH gas components, said gap-fill layer having a second thickness, as measured in one or more gaps between said conductors, greater than or approximately equal to said first thickness, thereby planarizing said interconnection layer over said high aspect ratio conductors; and (d) planarizing said interconnection layer over said low aspect ratio conductors by a chemical-mechanical polishing process to provide a top dielectric surface which is at least 50% of said first thickness above the tops of said conductors, whereby said seed layer is used to prevent said dc-bias sputtering from sputtering material from said conductors, and whereby decreased deposition thickness and decreased polish time are required to obtain a desired final dielectric thickness and planarity.