US5493687A
Expired / Lapsed
US
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RISC microprocessor architecture implementing multiple typed register sets
Assignee: Hanger Solutions LLC
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Filing: 1991-07-08
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Granted: 1996-02-20
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Expires: 2011-07-08
Abstract
Abstract A register system for a data processor which operates in a plurality of modes. The register system provides multiple, identical banks of register sets, the data processor controlling access such that instructions and processes need not specify any given bank. An integer register set includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow subset (RT[31:24]). While the data processor is in a first mode, instructions access the first and second subsets. While the data processor is in a second mode, instructions may access the first subset, but any attempts to access the second subset are re-routed to the shadow subset instead, transparently to the instructions, allowing system routines to seemingly use the second subset without having to save and restore data which user routines have written to the second subset. A re-typable register set provides integer width data and floating point width data in response to integer instructions and floating point instructions, respectively. Boolean comparison instructions specify particular integer or floating point registers for source data to be compared, and specify a particular Boolean register for the result, so there are no dedicated, fixed-location status flags. Boolean combinational instructions combine specified Boolean registers, for performing complex Boolean comparisons without intervening conditional branch instructions, to minimize pipeline disruption.
Inventors
- 👤 Sanjiv Garg
- 👤 Derek J. Lentz
- 👤 Le T. Nguyen
- 👤 Sho L. Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 14:18
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30189; G06F9/30003; G06F9/30007; G06F9/30029; G06F9/30036; G06F9/30098; G06F9/30105; G06F9/30112; G06F9/30116; G06F9/3012; G06F9/30123; G06F9/3013; G06F9/30138; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/38; G06F9/3836; G06F9/3851; G06F9/3885; G06F9/3888
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
161 words
In a data processing system, which includes a central processing unit (CPU) which performs operations according to an instruction, the operations operating upon integer data, a data register system comprising: a first register set including a plurality of first registers each for holding the integer data; a second register set including a plurality of second registers each for holding the integer data and for holding floating point data, wherein the instruction includes a field specifying which of the first and second register sets is to be accessed in response to the instruction; means, responsive to the field, for accessing the first register set or the second register set as specified by the field, including i) reading means for reading an operand value from either the first register set or second register set as specified by the field, and ii) writing mean for writing a result value to the first register set or the second register set as specified by the field.
Claim 2
Dependent Claim
161 words
In a data processing system, which includes a central processing unit (CPU) which performs operations according to an instruction, the operations operating upon integer data, a data register system comprising: a first register set including a plurality of first registers each for holding the integer data; a second register set including a plurality of second registers each for holding the integer data and for holding floating point data, wherein the instruction includes a field specifying which of the first and second register sets is to be accessed in response to the instruction; means, responsive to the field, for accessing the first register set or the second register set as specified by the field, including i) reading means for reading an operand value from either the first register set or second register set as specified by the field, and ii) writing mean for writing a result value to the first register set or the second register set as specified by the field.
Claim 3
Dependent Claim
21 words
The apparatus of claim 1, wherein said first and second register sets each have two write ports and five read ports.
Claim 4
Independent Claim
340 words
An apparatus comprising: execution means for executing instructions, the instructions performing operations upon operands to generate results, each instruction specifying a respective source address for each operand and a destination address for the result of the instruction, each address specifying a register set and an offset; a first register set including a plurality of individually addressable registers each for storing integer values; first access means for writing and reading values to and from the first register set according to a given instruction, the first access means including, i) first reading means, responsive to the given instruction having a given source address which specifies the first register set as a source for an operand of the given instruction, for reading the operand's value from the first register set at the offset specified by the given source address, and ii) first writing means, responsive to the given instruction having a given destination address which specifies the first register set as a destination for the result of the given instruction, for writing the result's value to the first register set at the offset specified by the given destination address; a second register set including a plurality of individually addressable registers, wherein each addressable register is configured to store floating point values and integer values; and second access means for writing and reading integer and floating point values to and from the second register set according to the given instruction, the second access means including, i) second reading means, responsive to the given instruction having a given source address which specifies the second register set as a source for an operand of the given instruction, for reading the operand's value from the second register set at the offset specified by the given source address, and ii) second writing means, responsive to the given instruction having a given destination address which specifies the second register set as a destination for the result of the given instruction, for writing the result's value to the second register set at the offset specified by the given destination address.
Claim 5
Independent Claim
340 words
An apparatus comprising: execution means for executing instructions, the instructions performing operations upon operands to generate results, each instruction specifying a respective source address for each operand and a destination address for the result of the instruction, each address specifying a register set and an offset; a first register set including a plurality of individually addressable registers each for storing integer values; first access means for writing and reading values to and from the first register set according to a given instruction, the first access means including, i) first reading means, responsive to the given instruction having a given source address which specifies the first register set as a source for an operand of the given instruction, for reading the operand's value from the first register set at the offset specified by the given source address, and ii) first writing means, responsive to the given instruction having a given destination address which specifies the first register set as a destination for the result of the given instruction, for writing the result's value to the first register set at the offset specified by the given destination address; a second register set including a plurality of individually addressable registers, wherein each addressable register is configured to store floating point values and integer values; and second access means for writing and reading integer and floating point values to and from the second register set according to the given instruction, the second access means including, i) second reading means, responsive to the given instruction having a given source address which specifies the second register set as a source for an operand of the given instruction, for reading the operand's value from the second register set at the offset specified by the given source address, and ii) second writing means, responsive to the given instruction having a given destination address which specifies the second register set as a destination for the result of the given instruction, for writing the result's value to the second register set at the offset specified by the given destination address.
Claim 6
Dependent Claim
68 words
The apparatus of claim 3, wherein: a given instruction may specify a first and a second source address and a destination address, with each address specifying either of the first or second register sets such that the given instruction requires access to both register sets; and the first and second access means operate simultaneously to provide the instruction parallel access to both the first and second register sets.
Claim 7
Dependent Claim
21 words
The apparatus of claim 2, wherein said first and second register sets each have two write ports and five read ports.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |