EP0170284A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Microcomputer
Assignee: NEC Corp
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Filing: 1985-08-02
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Granted: —
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Expires: 2005-08-02
Abstract
Abstract 1. A microcomputer including a plurality of register banks in which different register banks can be accessible during the execution of one instruction is disclosed. The microcomputer comprises a plurality of register banks each consisting of a plurality ot registers for containing data therein, a bank address register for holding the address of one of said register banks to be accessed and access control means responsive to a bank address signal for putting one of said register banks in accessible condition. The microcomputer is characterized by further comprising: a logic gate circuit receiving at one input at least one bit of the address held in the bank address register and at another input a predetermined portion of the code of an instruction to be executed by the microcomputer and for modifying the inputted bit of the bank address; and a selection circuit for selecting any one of the modified bit and the non-modified bit of the bank address and outputting the selected bit as at least a portion of the bank address signal to said access control means.
Inventors
- 👤 Yoshitaka Kitada
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 18:53
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30098; G06F9/3012; G06F9/30138; G06F9/46; G06F9/461; G06F9/462
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
150 words
A microcomputer which includes a plurality of register banks each consisting of a plurality of registers for containing data therein, a bank address register for holding the address of one of said register banks to be accessed and access control means responsive to a bank address signal for putting one of said register banks in accessible condition, said microcomputer comprising: a logic gate circuit receiving at one input at least one bit of the address held in the bank address register and at another input a predetermined portion of the code of an instruction to be executed by the microcomputer and for modifying the inputted bit of the bank address; and a selection circuit for selecting any one of the modified bit and the non-modified bit of the bank address and outputting the selected bit as at least a portion of the bank address signal to said access control means.
Claim 2
Dependent Claim
150 words
A microcomputer which includes a plurality of register banks each consisting of a plurality of registers for containing data therein, a bank address register for holding the address of one of said register banks to be accessed and access control means responsive to a bank address signal for putting one of said register banks in accessible condition, said microcomputer comprising: a logic gate circuit receiving at one input at least one bit of the address held in the bank address register and at another input a predetermined portion of the code of an instruction to be executed by the microcomputer and for modifying the inputted bit of the bank address; and a selection circuit for selecting any one of the modified bit and the non-modified bit of the bank address and outputting the selected bit as at least a portion of the bank address signal to said access control means.
Claim 3
Dependent Claim
18 words
A microcomputer as claimed in Claim 1, wherein said logic gate circuit is constituted by an OR gate.
Claim 4
Dependent Claim
19 words
A microcomputer as claimed in Claim 1, wherein the address of the register bank is expressed in two bits.
Claim 5
Dependent Claim
96 words
A microcomputer as claimed in Claim 3, wherein the logic gate circuit comprises a first OR gate receiving at one input the least significant bit of the address held in the bank address register and at another input the least significant bit of the code of an instruction to be executed by the microcomputer and a second OR gate receiving at one input the most significant bit of the address held in the bank address register and at another input the least significant bit of the code of the instruction to be executed by the microcomputer.
Claim 6
Dependent Claim
78 words
A microcomputer as claimed in Claim 4 , wherein the selection circuit comprises a first selection circuit receiving the output of the first OR gate and the least significant bit of the address held in the bank address register and for selecting any one thereof, and a second selection circuit receiving the output of the second OR gate and the most significant bit of the address held in the bank address register and for selecting any one thereof.
Claim 7
Dependent Claim
30 words
A microcomputer as claimed in Claim 5, wherein the first and second selection circuits are responsive to the variation of a timing signal to select one of the inputted signals.
Claim 8
Dependent Claim
17 words
A microcomputer as claimed in Claim 1, wherein the instruction code has a length of 8 bits.
Claim 9
Dependent Claim
20 words
A microcomputer as claimed in Claim 1 , wherein said logic gate circuit is constituted by an Exclusive OR gate.
Claim 10
Dependent Claim
48 words
A microcomputer as claimed in Claim 8, wherein the Exclusive OR gate receives at one input the bit 0 of the address held in the bank address register and at another input the least significant bit of the code of an instruction to be executed by the microcomputer.
Claim 11
Dependent Claim
19 words
A microcomputer as claimed in Claim 9, wherein the address of the register bank is expressed in two bits.
Claim 12
Dependent Claim
28 words
A microcomputer as claimed in Claim 9, wherein the selection circuit is responsive to the variation of a timing signal to select one of the two inputted signals.
Claim 13
Dependent Claim
17 words
A microcomputer as claimed in Claim 9, wherein the instruction code has a length of 8 bits.
Claim 14
Dependent Claim
115 words
A microcomputer which includes a plurality of register banks each consisting of a plurality of registers for containing data therein, a bank address register for generating the address of one of said register banks to be accessed and access control means responsive to a bank address signal for putting one of said register banks in accessible condition, said access control means comprising: first means for receiving the address of said address register; second means for receiving information indicating a different register bank to be selected; third means responsive to said address and said information for generating an actually selecting signal; and fourth means for applying said actually selecting signal to one of said register banks.
Claim 15
Dependent Claim
115 words
A microcomputer which includes a plurality of register banks each consisting of a plurality of registers for containing data therein, a bank address register for generating the address of one of said register banks to be accessed and access control means responsive to a bank address signal for putting one of said register banks in accessible condition, said access control means comprising: first means for receiving the address of said address register; second means for receiving information indicating a different register bank to be selected; third means responsive to said address and said information for generating an actually selecting signal; and fourth means for applying said actually selecting signal to one of said register banks.
References Cited (Backward Citations)
No citation records indexed.
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