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EP0454636A1 Expired / Lapsed EP ⏱️ 0.0 years remaining

Method for carrying out a boolean operation between any two bits of any two registers

Assignee: STMicroelectronics SRL
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Filing: 1991-04-24
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Granted: —
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Expires: 2011-04-24
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Abstract

Abstract A method for performing logic operations between any two bits belonging respectively to any two distinct registers belonging to a register file and/or to other physical data storing resources of a microprocessor or of internal and/or external pheripherals associated with the microprocessor, employs procedures which permit the utilization of the entire register addressing space. The method permits to the microprocessor to perform as a real boolean processor for simulating complex logic networks in an efficient and fast manner.

Inventors

  • 👤 Flavio Scarra'

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 00:15
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30029

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 600 words
A method for performing logic operations between a first and a second bit, selected respectively from the bits stored in any two distinct registers belonging to a register file or to any other data storing physical device of a microprocessor or of internal and/or external peripherals associated with said microprocessor, characterized by comprising at least one of the following steps or combination thereof: a) selecting a first bit (j) in a first source register (r s ) and a second bit (i) in a second destination register (r d ); placing said first bit in a logic XOR with said second bit and writing the resulting bit into the position occupied by said second bit in said second destination register, without altering the other bits present in said destination register; b) selecting a first bit (j) in a first source register (r s ); generating the complementary bit of said first bit; placing said complementary bit of said first bit in a logic XOR with a second bit (i) selected from the bits stored in a second destination register (r d ) and writing the resulting bit in the position occupied by said second bit in said second destination register, without altering the other bits stored in said destination register; c) selecting a first bit (j) in a first source register (r s ) and a second bit (i) in a second destination register (r d ), placing said first bit in a logic AND with said second bit and writing the resulting bit in the position occupied by said second bit in said second destination register, without altering the other bits stored in said destination register; d) selecting a first bit (j) in a first source register (r s ) and a second bit (i) in a second destination register (r d ), generating a complementary bit of said first bit and placing said complementary bit in a logic AND with said second bit and writing the resulting bit in the position occupied by said second bit in said second destination register, without altering the other bits stored in said destination register; e) selecting a first bit (j) in a first source register (r s ) and a second bit (i) in a second destination register (r d ), placing said first bit in a logic OR with said second bit and writing the resulting bit in the position occupied by said second bit in said second destination register, without altering the other bits stored in said destination register; f) selecting a first bit (j) in a first source register (r s ) and a seocnd bit (i) in a second destination register (r d ), generating a complementary bit of said first bit and placing said complementary bit in a logic OR with said second bit and writing the resulting bit in the position occupied by said second bit in said second destination register, without altering the other bits stored in said destination register; g) selecting a first bit (j) in a first source register (r s ), and writing said first bit in the position occupied by a second bit (i) selected in a second destination register (r d ), without altering the other bits stored in said second destination register; h) selecting a first bit (j) in a first source register (r s ), generating a complementary bit of said first selected bit and writing said complementary bit in the position occupied by a second selected bit (i) in a second destination register (r d ), without altering the other bits stored in said destination register.
Claim 2
Dependent Claim 122 words
The method according to claim 1, wherein each of said steps a), b), c), d), e) and f) comprise: - carrying out a Set or a Reset operation on said selected bit of the data stored in said destination register in function of the type of operator of said logic operation and storing the resulting modified data in a temporary storage register; - performing a ZERO TEST on said selected bit of said source register; - saving said modified data stored in said temporary storage register to said destination register in function of the result of said ZERO TEST, thus completing the logic operation between said selected bits without altering any other bits in either one of said source and destination registers.
Claim 3
Dependent Claim 131 words
The method according to claim 1, wherein each of said steps g) and h) comprise: - carrying out a ZERO TEST on said selected bit of said source register; - carrying out a Set operation on said selected bit of the data stored in said destination register and storing the modified data in a temporary storage register; - carrying out a Reset operation on the same selected bit of said modified data saved to said temporary storage register in function of the result of said ZERO TEST carried out on the selected bit of the source register; - eventually saving the manipulated data stored in said temporary storage register to said destination register for completing a Bit Load operation, without affecting any other bits stored in said source and destination registers.
Claim 4
Independent Claim 136 words
A method of manipulating data in a microprocessor having a plurality of registers associated therewith, for performing a logic operation between a first bit selected from the bits stored in a source register and a second bit selected from the bits stored in a destination register distinct from the source register, comprising the steps of performing Set/Reset operations on said selected bit of the destination register; storing the modified data of said destination register in a temporary storage register; eventually saving to said destination register the modified data temporarily stored in said register; all in function of certain parameters determined by the type of logic operator involved in said logic operation between said selected bits and by the value of said selected bit of the source register, all without affecting any other bits in either register.

References Cited (Backward Citations)

US4212076A Cited
US4331893A Cited
EP0408464A2 Cited

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