Method and apparatus for upgrading a data processing system from a single processor system to a multiprocessor system

Claim 2

A data processing system, comprising: a first central processing unit (CPU); an expansion port into which a second CPU chip may be directly inserted; a plurality of data buses; a first CPU control port coupled to one of said data buses and associated with said first CPU, said first CPU control port for receiving and interrupt request signals from and transmitting interrupt request signals to said expansion port when said second CPU is inserted therein; a bus controller coupled to said plurality of data buses, said bus controller comprising: a first coprocessor interface coupled to said first CPU, said first coprocessor interface generating an interrupt request signal in response to a first coprocessor error signal; an arbitrator coupled to said first coprocessor interface for receiving and arbitrating interrupt request signals from said first coprocessor interface and said first CPU control port; and an interrupt controller coupled to said arbitrator for determining the priority of a plurality of interrupt request signals and transmitting an interrupt command to said first CPU in response thereto; a second CPU control port coupled to one of said data buses and associated with said expansion port, said second CPU control port for receiving interrupt request signals from said first CPU and transmitting interrupt request signals to said expansion port when said second CPU is inserted therein; and a second coprocessor interface coupled to said expansion port, said second coprocessor interface generating an interrupt request signal in response to a second coprocessor error signal; wherein said data processing system is operable to run as a single processor system when said expansion port is empty, and a multiple processor system when said second CPU is inserted in said expansion port.

Claim 3

The data processing system of claim 1 wherein the first and second CPUs comprise semiconductor microprocessors.

Claim 4

The data processing system of claim 1 wherein the plurality of data buses comprise a CPU bus, a local bus, an expansion bus, and an internal peripheral bus.

Claim 5

The data processing system of claim 3 wherein the internal peripheral bus comprises an XD bus, and the expansion bus is from the group consisting of an EISA bus, an ISA bus, and a VESA bus.

Claim 6

The data processing system of claim 3 wherein the first CPU and the expansion port are coupled to said CPU data bus, the first and second CPU control ports are coupled to said internal peripheral bus, and said bus controller is coupled to said local bus, said expansion bus, and said internal peripheral bus.

Claim 7

The data processing system of claim 3 further comprising: a system controller coupled to said local bus; and a processor transferring circuit coupled to said system controller and said CPU bus, said processor transferring circuit for enabling said system controller to communicate with only one of said first and second CPUs at any one time when said second CPU is inserted into said expansion port.

Claim 8

The data processing system of claim 6 further comprising: a system memory coupled to said local bus and controlled by said system controller; and a system cache coupled to said local bus and controlled by said system controller.

Claim 9

The data processing system of claim 3 further comprising an interrupt vector port coupled to said internal peripheral bus for storing interrupt vectors associated with said expansion port when said second CPU is inserted therein.

Claim 10

The data processing system of claim 3 further comprising a coprocessor coupled to said CPU bus for generating a third coprocessor error signal.

Claim 11

The data processing system of claim 3 further comprising at least one peripheral device coupled to the expansion bus.

Claim 12

The data processing system of claim 3 further comprising a ROM BIOS coupled to the internal peripheral bus.

Claim 13

The data processing system of claim 1 wherein said first coprocessor interface is coupled to said first CPU by means of a first coprocessor error signal line and a first error ignore signal line, and said second coprocessor interface is coupled to said expansion port by means of a second coprocessor error signal line and a second error ignore signal line.

Claim 14

The data processing system of claim 1 wherein said expansion port comprises a CPU chip socket positioned on a circuit board on which said first CPU is also positioned.

Claim 15

A data processing system, comprising: a first central processing unit (CPU); an expansion port into which a second CPU chip may be directly inserted; a CPU bus coupled to said first CPU and said expansion port; a CPU/local bus interface; a local bus coupled to said CPU bus by means of said CPU/local bus interface; a local/expansion bus interface; an expansion bus coupled to said local bus by means of said local/expansion bus interface; an expansion/peripheral bus interface; an internal peripheral bus coupled to said expansion bus by means of said expansion/peripheral bus interface; a first CPU control port coupled to said internal peripheral bus and associated with said first CPU, said first CPU control port for receiving interrupt request signals from and transmitting interrupt request signals to said expansion port when said second CPU is inserted therein; a bus controller coupled to said local bus, said expansion bus, and said internal peripheral bus, said bus controller comprising: a first coprocessor interface coupled to said first CPU by means of a first coprocessor error signal line and a first error ignore signal line, said first coprocessor interface generating an interrupt request signal in response to a first coprocessor error signal; an arbitrator coupled to said first coprocessor interface for receiving and arbitrating interrupt request signals from said first coprocessor interface and said first CPU control port; and an interrupt controller coupled to said arbitrator for determining the priority of a plurality of interrupt request signals and transmitting an interrupt command to said first CPU in response thereto; a second CPU control port coupled to said internal peripheral bus and associated with said expansion port, said second CPU control port for receiving interrupt request signals from said first CPU and transmitting interrupt request signals to said expansion port when said second CPU is inserted therein; a second coprocessor interface coupled to said expansion port by means of a second coprocessor error signal line and a second error ignore signal line, said second coprocessor interface generating an interrupt request signal in response to a second coprocessor error signal; a system controller coupled to said local bus; and a processor transferring circuit coupled to said system controller and said CPU bus, said processor transferring circuit for enabling said system controller to communicate with only one of said first and second CPUs at any one time when said second CPU is inserted into said expansion port; wherein said data processing system is operable to run as a single processor system when said expansion port is empty, and a multiple processor system when said second CPU is inserted in said expansion port.

Claim 16

A data processing system, comprising: a first central processing unit (CPU); an expansion port into which a second CPU chip may be directly inserted; a CPU bus coupled to said first CPU and said expansion port; a CPU/local bus interface; a local bus coupled to said CPU bus by means of said CPU/local bus interface; a local/expansion bus interface; an expansion bus coupled to said local bus by means of said local/expansion bus interface; an expansion/peripheral bus interface; an internal peripheral bus coupled to said expansion bus by means of said expansion/peripheral bus interface; a first CPU control port coupled to said internal peripheral bus and associated with said first CPU, said first CPU control port for receiving interrupt request signals from and transmitting interrupt request signals to said expansion port when said second CPU is inserted therein; a bus controller coupled to said local bus, said expansion bus, and said internal peripheral bus, said bus controller comprising: a first coprocessor interface coupled to said first CPU by means of a first coprocessor error signal line and a first error ignore signal line, said first coprocessor interface generating an interrupt request signal in response to a first coprocessor error signal; an arbitrator coupled to said first coprocessor interface for receiving and arbitrating interrupt request signals from said first coprocessor interface and said first CPU control port; and an interrupt controller coupled to said arbitrator for determining the priority of a plurality of interrupt request signals and transmitting an interrupt command to said first CPU in response thereto; a second CPU control port coupled to said internal peripheral bus and associated with said expansion port, said second CPU control port for receiving interrupt request signals from said first CPU and transmitting interrupt request signals to said expansion port when said second CPU is inserted therein; a second coprocessor interface coupled to said expansion port by means of a second coprocessor error signal line and a second error ignore signal line, said second coprocessor interface generating an interrupt request signal in response to a second coprocessor error signal; a system controller coupled to said local bus; and a processor transferring circuit coupled to said system controller and said CPU bus, said processor transferring circuit for enabling said system controller to communicate with only one of said first and second CPUs at any one time when said second CPU is inserted into said expansion port; wherein said data processing system is operable to run as a single processor system when said expansion port is empty, and a multiple processor system when said second CPU is inserted in said expansion port.

Claim 17

The data processing system of claim 14 wherein the first and second CPUs comprise semiconductor microprocessors.

Claim 18

The data processing system of claim 14 wherein the internal peripheral bus comprises an XD bus, and the expansion bus is from the group consisting of an EISA bus, an ISA bus, and a VESA bus.

Claim 19

The data processing system of claim 14 further comprising: a system memory coupled to said local bus and controlled by said system controller; and a system cache coupled to said local bus and controlled by said system controller.

Claim 20

The data processing system of claim 14 further comprising an interrupt vector port coupled to said internal peripheral bus for storing interrupt vectors associated with said expansion port when said second CPU is inserted therein.

Claim 21

The data processing system of claim 14 further comprising a coprocessor coupled to said CPU bus for generating a third coprocessor error signal.

Claim 22

The data processing system of claim 14 further comprising at least one peripheral device coupled to the expansion bus.

Claim 23

The data processing system of claim 14 further comprising a ROM BIOS coupled to the internal peripheral bus.

Claim 24

The data processing system of claim 14 wherein said expansion port comprises a CPU chip socket positioned on a circuit board on which said first CPU is also positioned.

Claim 27

A data processing system, comprising: a first central processing unit (CPU); at least one expansion port into which at least one additional CPU chip may be directly inserted; a system controller; and interrupt circuitry coupled to said first CPU, said at least one expansion port, and said system controller, said interrupt circuitry being configured to allow the data processing system to operate as a multiple processor system when said at least one additional CPU chip is directly inserted in said expansion port and as a single processor system when said expansion port is empty, only one of said first and said at least one additional CPU communicating with said system controller at any one time.

Claim 28

A data processing system, comprising: a first central processing unit (CPU); at least one expansion port into which at least one additional CPU chip may be directly inserted; a system controller; and interrupt circuitry coupled to said first CPU, said at least one expansion port, and said system controller, said interrupt circuitry being configured to allow the data processing system to operate as a multiple processor system when said at least one additional CPU chip is directly inserted in said expansion port and as a single processor system when said expansion port is empty, only one of said first and said at least one additional CPU communicating with said system controller at any one time.

Claim 29

The data processing system of claim 24 wherein said at least one expansion port comprises at least one CPU chip socket positioned on a circuit board on which said first CPU is also positioned.