EP0529142A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Upgradeable/downgradeable computers
Assignee: Acer Inc
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Filing: 1991-08-30
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Granted: —
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Expires: 2011-08-30
Abstract
Abstract A upgradeable/downgradeable data processing system capable of operating with different types of central processing units (CPU). The system has a first socket for plugging with a first CPU and a second socket for plugging with a second CPU. Means are provided for preventing possible signal contention between the first and second CPU, and for synchronizing clocks for operating a CPU with the system clock. Means are also provided for interfacing to coprocessor of the different types of CPU as well as for adjusting the signals to and from the CPU to the signal width of the system.
Inventors
- 👤 Hung-Ta 5F No. 8 Huang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 15:48
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3877; G06F9/3879; G06F13/00; G06F13/38; G06F13/40; G06F13/4063; G06F13/4068
Claims Analysis
Total Claims: 41
Claim 1
Independent Claim
212 words
A data processing system capable of operating with different types of central processing units (CPU), said different types of CPU capable of having different operating frequencies and addressing data differently the data processing system comprising: (a) a first CPU socket for insertion with a first CPU; (b) a second CPU socket for insertion with a second CPU; (c) an interface control circuit for controlling interfacing between said CPU external devices of said system, said interface control circuit operating with a system clock; (d) means for generating a first CPU clock to said first CPU socket and a second CPU clock to said second CPU socket; (e) means coupled to said first CPU socket and said second CPU socket for detecting presence of an inserted CPU in said data processing system; (f) means coupled to said detecting means and responsive to presence of both said first CPU and said second CPU being inserted into said data processing system for activating one CPU and deactivating other one of said CPU in accordance with a predetermined sequence; (g) means for synchronizing said CPU clock of said activated CPU with the system clock; and (h) means for adapting address signals from an activated CPU to enable said CPU to address data in said data processing system.
Claim 2
Dependent Claim
39 words
A data processing system as in claim 1, wherein said first CPU and second CPU being capable of having a coprocessor and said data processing system further comprises means for processing errors of said coprocessor of said activated CPU.
Claim 3
Dependent Claim
18 words
A data processing system as in claim 1, wherein a CPU being deactivated by being put into HOLD.
Claim 4
Dependent Claim
21 words
A data processing system as in claim 1, further comprises means for inhibiting a subset of outputs of a deactivated CPU.
Claim 5
Dependent Claim
94 words
A data processing system capable of operating with different types of central processing units (CPU), comprising: (a) a first CPU socket for insertion with a first CPU; (b) a second CPU socket for insertion with a second CPU; (c) means for generating a system clock for operating said data processing system; and (d) means for generating a CPU clock for operating an inserted CPU, comprising: (i) means for generating a reset signal for resetting a CPU; and (ii) means for providing synchronization between said system clock with said CPU clock using said reset signal.
Claim 6
Dependent Claim
49 words
A system as in claim 5, wherein said synchronization means comprises means for delaying reset signal to produce a delayed reset signal and means providing synchronization between said CPU clock and said system clock during a time period between activation of said reset signal and said delayed reset signal.
Claim 7
Dependent Claim
18 words
A system as in claim 6, wherein said synchronization means comprises a delay circuit and a inverter circuit.
Claim 8
Dependent Claim
30 words
A system as in claim 5, wherein said system clock having a first frequency and said CPU clock having a second frequency which is a multiple of said first frequency.
Claim 9
Dependent Claim
40 words
A system as in claim 5, further comprising means for detecting stabilization of power in said data processing system and wherein means for generating said reset signal operates in response to a stabilization of power in said data processing system.
Claim 10
Dependent Claim
93 words
In a data processing system having a first CPU socket for insertion with a first CPU and a second CPU socket for insertion with second CPU, means for enabling the system to operate with different types of central processing units (CPU) capable of having different frequencies, comprising: (a) means for generating a system reset signal; (b) means for generating a system clock for operating said data processing system; (c) means for generating a CPU clock for operating an inserted CPU, (b) means for providing synchronization between said system clock and said CPU clock.
Claim 11
Dependent Claim
48 words
A system as in claim 10, wherein said synchronization means comprises means for delaying reset signal to produce a delayed reset signal and means synchronizing between said system clock and said CPU clock during a time period between activation of said reset signal and said delayed reset signal.
Claim 12
Dependent Claim
18 words
A system as in claim 11, wherein said synchronizing means comprises a delay circuit and a inverter circuit.
Claim 13
Dependent Claim
30 words
A system as in claim 10, wherein said system clock having a first frequency and said second clock having a second frequency which is a multiple of said first frequency.
Claim 14
Dependent Claim
40 words
A system as in claim 13, further comprising means for detecting stabilization of power in said data processing system and wherein means for generating said reset signal operates in response to a stabilization of power in said data processing system.
Claim 15
Dependent Claim
73 words
The system as in claim 10, wherein said means for generating said CPU clock comprises means for delaying said system reset to generate a delayed system reset signal and wherein said synchronization being performed by extending a period of said CPU clock using said system reset signal, wherein said means for extending a clock period comprises inverting means for inverting said system reset signal and delay means for delaying said system reset signal.
Claim 16
Dependent Claim
38 words
The system as in claim 10, further comprises a power detection means generating an indication signal for indicating stabilization of power in said system and wherein said system reset signal being generated in response to said indication signal.
Claim 17
Dependent Claim
127 words
In a data processing system capable of operating with different types of central processing unit (CPU), the system having a first CPU socket for insertion with a first CPU and a second CPU socket for insertion with a second CPU, means in the system for enabling the system to operate with CPU having different frequencies: (a) means for generating an indication signal indicating stabilization of power supplied to said system; (b) means for generating a first clock; (c) an interface controller, responsive to said first clock for generating a second clock and responsive to stabilization indication signal to generate a reset signal; and (d) a clock generator responsive to said second clock and said reset signal for generating a third clock in synchronization with said second clock.
Claim 18
Dependent Claim
112 words
In a data processing system having a first socket for insertion with a first CPU and a second socket for insertion with a second CPU, means for enabling the system to operate with CPU having different frequencies: (a) means for generating an indication signal indicating stabilization of power in said system, (b) means for generating a first clock, (c) interface control means responsive to said first clock for generating a second clock and responsive to said stabilization indication signal for generating a reset signal, and (d) clock generator responsive to said second clock and said reset signal for generating a third clock and a fourth clock in synchronization with said third clock.
Claim 19
Dependent Claim
137 words
A data processing system capable of operating with different types of central processing unit (CPU), the system comprising: (a) a first CPU socket for insertion with a CPU, (b) a second CPU socket for insertion with a CPU, (c) detection means for detecting presence of said second CPU in said second CPU clock, (d) sequencer means comprising: i. means for generating a reset signal to said first CPU socket and a reset signal to said second CPU socket, ii. means responsive to presence of a CPU in each of the two CPU sockets for generating a signal to said first CPU socket for putting said CPU in said first CPU socket to HOLD, iii. means responsive to said CPU in said first CPU socket being in HOLD for enabling said second CPU to enter into normal operation.
Claim 20
Dependent Claim
47 words
A system as in claim 19, wherein said sequencer means further comprises means for putting said second CPU to HOLD and wherein said means for putting a CPU in said first CPU socket to HOLD operates in response to said second CPU having been put to HOLD.
Claim 21
Dependent Claim
30 words
A system as in claim 19, further comprising means for detecting power stabilization in said system and wherein said sequencer means being initiated by stabilization of power in said system.
Claim 22
Dependent Claim
37 words
A system as in claim 19, wherein said system further comprising an interface controller for controlling interfacing between said CPU and external devices of said system and wherein said HOLD signal being generated by said interface controller.
Claim 23
Dependent Claim
39 words
A system as in claim 22, wherein a CPU generating a HOLD ACKNOWLEDGE signal in response to being put to HOLD and further comprising means for sending a HOLD ACKNOWLEDGE signal from a selected CPU to said interface controller.
Claim 24
Dependent Claim
138 words
A data processing system capable of operating with different types of central processing unit (CPU), the system comprising: (a) a first CPU socket for insertion with a first CPU, (b) a second CPU socket for insertion with a second CPU, (c) means for providing selection between one of said first CPU in said first CPU socket and said second CPU in said second CPU socket as a preferred CPU of said system (d) sequencer means comprising: (i) means for generating a reset signal to said first CPU socket and a reset signal to said second CPU socket, (ii) means responsive to said selection means for generating a signal to a non-selected CPU socket for putting said CPU to HOLD, (iii) means responsive said non-selected CPU being in HOLD for enabling said selected CPU to enter into normal operation.
Claim 25
Dependent Claim
43 words
A system as in claim 24, wherein said sequencer means further comprises means for putting said selected CPU to HOLD and wherein said means for putting said non-selected CPU to HOLD operates in response to said selected CPU having been put to HOLD.
Claim 26
Dependent Claim
30 words
A system as in claim 25, further comprising means for detecting power stabilization in said system and wherein said sequencer means being initiated by stabilization of power in said system.
Claim 27
Dependent Claim
37 words
A system as in claim 24, wherein said system further comprising an interface controller for controlling interfacing between said CPU and external devices of said system and wherein said HOLD signal being generated by said interface controller.
Claim 28
Dependent Claim
39 words
A system as in claim 27, wherein a CPU generating a HOLD ACKNOWLEDGE signal in response to being put to HOLD and further comprising means for sending a HOLD ACKNOWLEDGE signal from a selected CPU to said interface controller.
Claim 29
Dependent Claim
127 words
In a data processing system having a first CPU socket for insertion with a CPU and a second CPU socket for insertion with a CPU, a method for facilitating operation of the system capable of being inserted with two CPUs, comprising the steps of: (a) detecting presence of said a CPU in said second CPU socket, (b) generating a reset signal to said first CPU socket and a reset signal to said second CPU socket, (c) generating a signal to said first CPU socket, in response to presence of said second CPU, to put a CPU in said first CPU socket to HOLD, and (d) enabling said second CPU to enter into normal operation in response to a CPU in said first CPU socket being in HOLD.
Claim 30
Dependent Claim
28 words
A method as in claim 29, further comprises a step of putting said CPU in said second CPU to HOLD before putting said first CPU socket to HOLD.
Claim 31
Dependent Claim
120 words
A data processing system capable of operating with different types of central processing units (CPU), the system comprising: (a) a first CPU socket for insertion with a CPU of a first type, said first type of CPU capable of having an internal coprocessor; (b) a second CPU socket for insertion with a CPU of a second type, said second type of CPU capable of having an external coprocessor; (c) a coprocessor socket for insertion with an external coprocessor for said second type of CPU; (d) a controller for controlling interfacing between said CPU and external devices of said system; (e) coprocessor interface means for interfacing said controller to said first CPU socket, said second CPU socket and said coprocessor socket.
Claim 32
Dependent Claim
37 words
A data processing system as in claim 31, wherein said coprocessor interface comprises means for sending an indication signal to said controller when at least one of said first CPU socket and said coprocessor socket is populated.
Claim 33
Dependent Claim
37 words
A data processing system as in claim 31, wherein said coprocessor interface comprises means for selectively sending a status signal from one of said first CPU socket and said coprocessor in said coprocessor socket to said controller.
Claim 34
Dependent Claim
16 words
A data processing system as in claim 33, wherein said status signal is an error signal.
Claim 35
Dependent Claim
111 words
A data processing system capable of operating with different types of central processing units (CPU) wherein different types of CPU is capable of addressing data differently, the system having a first CPU socket for insertion with a first CPU and a second CPU socket for insertion with a second CPU but wherein the system operates with only one of the first and second CPU, the data processing system comprising: (a) a memory; (b) a system bus for communicating data and address between said memory and an inserted CPU; and (c) means for converting addressing signals from an inserted CPU to enable said inserted CPU to address data using said system bus.
Claim 36
Dependent Claim
26 words
A data processing system as in claim 35, wherein said means for converting address signals further comprises means for forcing addressing signals into a predetermined pattern.
Claim 37
Dependent Claim
34 words
A data processing system as claim 36, wherein data are accessed by said CPU in more than one cycle and wherein addressing signals are forced in the first cycle during predetermined data access operations.
Claim 38
Dependent Claim
27 words
A data processing system as in claim 37, wherein said first cycle is indicated by a signal generated at the last cycle of the previous data access.
Claim 39
Dependent Claim
19 words
A data processing system as in claim 37, wherein said data access operations including a cacheable memory read cycle.
Claim 40
Dependent Claim
27 words
A data processing system as in claim 37, wherein said addressing signals include signals for forcing a CPU to access data having a predetermined number of bits.
Claim 41
Dependent Claim
200 words
A data processing system capable of operating with different types of central processing units (CPU) wherein different types of CPU being capable of addressing data differently, the data processing system comprising: (a) a memory; (b) a first CPU socket for insertion with a first CPU; (c) a second CPU socket for insertion with a second CPU; (d) a system bus for communicating data and address between said memory and first CPU and for communicating data and address between said memory and second CPU; (e) means for detecting presence of first CPU and second CPU; and (f) means, coupled to communicate address signals from said second CPU socket to said system bus, for inhibiting address signals from said second CPU socket to said system bus, comprising (i) first means for inhibiting said address signals from a CPU in said second CPU socket when said CPU in said second socket is inactive (in HOLD); (ii) second means for inhibiting said address signals from said second CPU socket when said a CPU in said first CPU socket is active (not in HOLD); and (iii) third means for inhibiting said address signals from said second CPU socket when said CPU socket is not populated.
References Cited (Backward Citations)
EP0351961A2
Cited
EP0411806A2
Cited
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