Patent US5493509A successfully refreshed from Google Patents.
US5493509A
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Method of and apparatus for generating mask layouts
Assignee: Toshiba Corp
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Filing: 1993-09-02
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Granted: 1996-02-20
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Expires: 2013-09-02
Abstract
Abstract In graphic data representing a symbolic layout for a semiconductor integrated circuit, a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles are set. First, the graphic data is cut along said first cutting lines to produce a plurality of first segment data items. These first segment data items are each compacted in the direction of the second cutting line. These compacted first segment data items are connected according to the first cutting lines. This connected first segment data is cut along the second cutting lines to produce a plurality of second segment data items. These second segment data items are each compacted in the direction of the first cutting line. These compacted second segment data items are connected to one another to produce a compacted mask layout.
Inventors
- 👤 Nobu Matsumoto
- 👤 Shojiro Mori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:10
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; G06F30/398
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
175 words
A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of: reading data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; cutting the data read from said second memory device along said first cutting lines to produce a plurality of first segment data items; compacting these first segment data items in the direction of the second cutting line; connecting these compacted first segment data items according to the first cutting lines; cutting the entire first segment data thus connected along the second cutting lines to produce a plurality of second segment data items; compacting these second segment data items in the direction of the first cutting line; and connecting these compacted second segment data items to each other and storing the resulting data in said first memory device.
Claim 2
Independent Claim
175 words
A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of: reading data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; cutting the data read from said second memory device along said first cutting lines to produce a plurality of first segment data items; compacting these first segment data items in the direction of the second cutting line; connecting these compacted first segment data items according to the first cutting lines; cutting the entire first segment data thus connected along the second cutting lines to produce a plurality of second segment data items; compacting these second segment data items in the direction of the first cutting line; and connecting these compacted second segment data items to each other and storing the resulting data in said first memory device.
Claim 3
Dependent Claim
20 words
A method according to claim 1, wherein said first cutting lines are set in the vertical direction of the data.
Claim 4
Dependent Claim
21 words
A method of according to claim 1, wherein said second cutting lines are set in the horizontal direction of the data.
Claim 5
Dependent Claim
16 words
A method of according to claim 1, wherein said first and second cutting lines contain bends.
Claim 6
Dependent Claim
33 words
A method of according to claim 1, wherein said compaction is achieved in parallel by a plurality of processors in a manner that treats a single segment data item as a single job.
Claim 7
Dependent Claim
27 words
A method according to claim 1, wherein each of said compacting steps compacts each of said first and second segment data items by a constraint graph method.
Claim 8
Independent Claim
161 words
A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of: reading graphic data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; cutting the data in said second memory device along said first cutting lines to produce a plurality of first segment data items; compacting these first segment data items in the direction of the second cutting line; cutting these compacted first segment data items along the second cutting lines to produce a plurality of second segment data items; compacting these second segment data items in the direction of the first cutting line; and connecting these compacted second segment data items to each other and storing the resulting data in said first memory device.
Claim 9
Independent Claim
161 words
A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of: reading graphic data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; cutting the data in said second memory device along said first cutting lines to produce a plurality of first segment data items; compacting these first segment data items in the direction of the second cutting line; cutting these compacted first segment data items along the second cutting lines to produce a plurality of second segment data items; compacting these second segment data items in the direction of the first cutting line; and connecting these compacted second segment data items to each other and storing the resulting data in said first memory device.
Claim 10
Dependent Claim
16 words
A method of according to claim 7, wherein said second cutting lines cut the data horizontally.
Claim 11
Dependent Claim
16 words
A method of according to claim 7, wherein said first and second cutting lines contain bends.
Claim 12
Dependent Claim
33 words
A method of according to claim 7, wherein said compaction is achieved in parallel by a plurality of processors in a manner that treats a single segment data item as a single job.
Claim 13
Dependent Claim
15 words
A method according to claim 7, wherein said first cutting lines cut the data vertically.
Claim 14
Independent Claim
177 words
An apparatus for generating mask layouts for semiconductor integrated circuits, comprising: first memory means for storing data representing a symbolic layout for a semiconductor integrated circuit, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; first generating means for reading said data from said first memory means and cutting the data along said first cutting lines to produce a plurality of first segment data items; first compacting means for compacting said first segment data in the direction of the second cutting line; first connecting means for connecting the first segment data items compacted by said compacting means according to the first cutting lines; second generating means for cutting the connected first segment data along the second cutting lines to produce a plurality of second segment data items; second compacting means for compacting said second segment data items in the direction of the first cutting line; and second connecting means for connecting the second segment data items compacted by said second compacting means.
Claim 15
Independent Claim
177 words
An apparatus for generating mask layouts for semiconductor integrated circuits, comprising: first memory means for storing data representing a symbolic layout for a semiconductor integrated circuit, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; first generating means for reading said data from said first memory means and cutting the data along said first cutting lines to produce a plurality of first segment data items; first compacting means for compacting said first segment data in the direction of the second cutting line; first connecting means for connecting the first segment data items compacted by said compacting means according to the first cutting lines; second generating means for cutting the connected first segment data along the second cutting lines to produce a plurality of second segment data items; second compacting means for compacting said second segment data items in the direction of the first cutting line; and second connecting means for connecting the second segment data items compacted by said second compacting means.
Claim 16
Dependent Claim
31 words
An apparatus according to claim 12, wherein each of said first and second compacting means is equipped to compact said first and second segment data items using a constraint graph method.
Claim 17
Dependent Claim
15 words
An apparatus according to claim 12, wherein said first and second cutting lines contain bends.
Claim 18
Dependent Claim
39 words
An apparatus according to claim 12, wherein said first and second compacting means have each a plurality of processors and each processor performs parallel processing in a manner that treats a single segment data item as a single job.
Claim 19
Dependent Claim
20 words
An apparatus according to claim 12, wherein said first cutting lines are set in the vertical direction of the data.
Claim 20
Dependent Claim
20 words
An apparatus according to claim 12, wherein said second cutting lines are set in the horizontal direction of the data.
Claim 21
Independent Claim
198 words
A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of: reading data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; cutting the data read from said second memory device along said first cutting lines to produce a plurality of first segment data items, each of said first segment data items being partitioned from each other; compacting these first segment data items in a direction of the second cutting lines; connecting these compacted first segment data items according to the first cutting lines; cutting the entire first segment data thus connected along the second cutting lines to produce a plurality of second segment data items, each of said second segment data items being partitioned from each other; compacting these second segment data items in a direction of the first cutting lines; and connecting these compacted second segment data items to each other and storing resulting data in said first memory device.
Claim 22
Independent Claim
198 words
A method of generating mask layouts for semiconductor integrated circuits using a design-supporting apparatus, comprising the steps of: reading data representing a symbolic layout for a semiconductor integrated circuit stored in a first memory device and storing the data in a second memory device, the data containing a plurality of first cutting lines and a plurality of second cutting lines crossing the first cutting lines at right angles; cutting the data read from said second memory device along said first cutting lines to produce a plurality of first segment data items, each of said first segment data items being partitioned from each other; compacting these first segment data items in a direction of the second cutting lines; connecting these compacted first segment data items according to the first cutting lines; cutting the entire first segment data thus connected along the second cutting lines to produce a plurality of second segment data items, each of said second segment data items being partitioned from each other; compacting these second segment data items in a direction of the first cutting lines; and connecting these compacted second segment data items to each other and storing resulting data in said first memory device.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-02-19 | 1999-08-21 | 2000-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-19 | 2003-08-21 | 2004-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-19 | 2007-08-21 | 2008-02-20 | $7700.00 | Window Closed / Lapsed |