Abstract An optimized translation lookaside buffer (TLB) utilizes a least-recently-used algorithm for determining the replacement of virtual-to-physical memory translation entries. The TLB is faster and requires less chip area for fabrication. In addition to speed and size, the TLB is also optimized since many characteristics of the TLB may be changed without significantly changing the overall layout of the TLB. A TLB generating program may thus be used as a design aid. The translation lookaside buffer includes a level decoding circuit which allows masking of a variable number of the bits of a virtual address when it is compared to values stored within the TLB. The masking technique may be used for indicating a TLB hit or miss of a virtual address to be translated, and may also be used for invalidating selected entries within the TLB. The TLB also implements a pipelining technique wherein a LRU comparator compares the least significant bits of a LRU counter at the same time when the most significant bits of the LRU counter are being incremented. Finally, an address decoder is provided within the TLB for indexing each slice during a test mode to check for malfunctions.
A translation lookaside buffer comprising: a plurality of first storage locations for storing virtual addresses, each of said virtual addresses comprising a plurality of bits; a plurality of second storage locations, each of said second storage locations for storing a physical address corresponding to one of said virtual addresses and for storing a plurality of mask bits corresponding to said one of said virtual addresses, there being an equal number of first and second storage locations; comparator means connected to said plurality of first storage locations for determining whether a particular virtual address is stored within one of said plurality of first storage locations; and masking means connected to said comparator means for masking selected individual ones of said bits of said virtual addresses stored in said first storage locations, said individual ones of said bits of said virtual addresses selected depending upon said plurality of stored mask bits in said second storage locations; wherein said masking means is selectively controllable to simultaneously mask a first set of the bits of a first virtual address during a single virtual-to-physical address lookup.
Claim 2
Dependent Claim
181 words
A translation lookaside buffer comprising: a plurality of first storage locations for storing virtual addresses, each of said virtual addresses comprising a plurality of bits; a plurality of second storage locations, each of said second storage locations for storing a physical address corresponding to one of said virtual addresses and for storing a plurality of mask bits corresponding to said one of said virtual addresses, there being an equal number of first and second storage locations; comparator means connected to said plurality of first storage locations for determining whether a particular virtual address is stored within one of said plurality of first storage locations; and masking means connected to said comparator means for masking selected individual ones of said bits of said virtual addresses stored in said first storage locations, said individual ones of said bits of said virtual addresses selected depending upon said plurality of stored mask bits in said second storage locations; wherein said masking means is selectively controllable to simultaneously mask a first set of the bits of a first virtual address during a single virtual-to-physical address lookup.
Claim 3
Dependent Claim
25 words
The translation lookaside buffer according to claim 1 wherein said masking means is also for flushing translation entries within a selected range of virtual addresses.
Claim 4
Dependent Claim
70 words
The translation lookaside buffer (TLB) according to claim 1, said TLB further comprising: a plurality of testing input lines for providing external signals to test the operation of the TLB; and an address decoder coupled to said plurality of first storage locations and also coupled to said plurality of testing input lines, said address decoder being usable to access said first storage locations through said plurality of testing input lines.