Fuse circuit with feedback disconnect

Claim 2

A circuit for defining a logic state in an integrated circuit, comprising: a first logic element having an input and an output; a fuse element having a first terminal and a second terminal wherein the first terminal is coupled to the input of said first logic element, said fuse element being selectively configured in a conducting or a non-conducting state between said first and second terminals; a first transistor having a control electrode and having a conduction path coupled between a first voltage source and the input of said first logic element, said conduction path of said first transistor being enabled or disabled responsive to the output of said first logic element; and a second transistor having a control electrode and having a conduction path coupled between the second terminal of said fuse element and a second voltage source such that said second voltage source is decoupled from said input of said first logic element if said fuse element is in said non-conductive state, said conduction path of said second transistor being enabled or disabled responsive to the output of said first logic element.

Claim 3

The circuit of claim 1 wherein said first logic element is a logic gate.

Claim 4

The circuit of claim 2 wherein said logic gate is an inverter.

Claim 5

The circuit of claim 1 wherein said first and second transistors are complementary transistors.

Claim 6

The circuit of claim 1 wherein said first transistor is a MOS transistor.

Claim 7

The circuit of claim 5 wherein said first transistor is a p-channel transistor.

Claim 8

The circuit of claim 1 wherein said second transistor is a MOS transistor.

Claim 9

The circuit of claim 7 wherein said second transistor is an n-channel transistor.

Claim 10

The circuit of claim 1 wherein said fuse element is a fuse.

Claim 11

The circuit of claim 9 wherein said fuse element is a polysilicon fuse.

Claim 12

The circuit of claim 1 further comprising a pass gate having an input and an output wherein said output is connected to the second terminal of said fuse element.

Claim 13

The circuit of claim 11 wherein said pass gate comprises a third transistor and a fourth transistor connected in parallel.

Claim 14

The circuit of claim 12 wherein said third and fourth transistors are complementary MOS transistors.

Claim 15

The circuit of claim 12 wherein said third transistor is an n-channel transistor.

Claim 16

The circuit of claim 12 wherein said fourth transistor is a p-channel transistor.

Claim 17

The circuit of claim 11 further comprising a fifth transistor having a conduction path placed in series with the conduction path of said second transistor between the second terminal of said fuse element and said second voltage source and having a control electrode connected to the control electrode of said fourth transistor of said pass gate.

Claim 18

The circuit of claim 16 wherein said fifth transistor is a MOS transistor.

Claim 19

The circuit of claim 17 wherein said fifth transistor is an n-channel transistor.

Claim 20

The circuit of claim 11 further comprising a second logic element having an input and an output wherein said output is connected to the input of said pass gate.

Claim 21

The circuit of claim 19 wherein said second logic element is a logic gate.

Claim 22

The circuit of claim 20 wherein said logic gate is a NAND gate.

Claim 23

The circuit of claim 19 wherein said second logic element is a decoding element.

Claim 24

The circuit of claim 22 wherein said decoding element is a row decoder.

Claim 27

The method of claim 24 wherein the step of selectively configuring a fuse element comprises the step of opening a fuse between said input terminal and the input to said circuit.

Claim 28

A circuit for isolating a signal path, comprising: circuit means for buffering an output signal; fuse means for selectively opening a connection between an input terminal and an input to said circuit means; first transistor switch means for connecting a first voltage, in response to the output signal applied thereto, to the input of the circuit means; and second transistor switch means for connecting a second voltage, in response to the output signal applied thereto, to the input to said circuit means, said second voltage being decoupled from the input terminal if said fuse means is in an open state.

Claim 29

A circuit for isolating a signal path, comprising: circuit means for buffering an output signal; fuse means for selectively opening a connection between an input terminal and an input to said circuit means; first transistor switch means for connecting a first voltage, in response to the output signal applied thereto, to the input of the circuit means; and second transistor switch means for connecting a second voltage, in response to the output signal applied thereto, to the input to said circuit means, said second voltage being decoupled from the input terminal if said fuse means is in an open state.

Claim 30

The circuit of claim 26 wherein said circuit means comprises a logic gate.

Claim 31

The circuit of claim 26 wherein said first and second transistor switch means comprise complementary MOS transistors.

Claim 32

The circuit of claim 28 wherein said first transistor is an n-channel transistor and said second transistor is a p-channel transistor.

Claim 33

A circuit for defining a logic state in an integrated circuit, comprising: a first logic element having an input and an output; a fuse element having a first terminal and a second terminal wherein the first terminal is coupled to the input of said first logic element, said fuse element being selectively configured in a conducting or a non-conducting state between said first and second terminals; circuitry for receiving a logic signal at said first terminal; a first transistor having a control electrode and having a conduction path coupled between a first voltage source and the input of said first logic element, said conduction path of said first transistor being enabled or disabled responsive to the output of said first logic element; and a second transistor having a control electrode and having a conduction path coupled between the second terminal of said fuse element and a second voltage source such that said second voltage source is decoupled from said input of said first logic element if said fuse element is in said non-conductive state, said conduction path of said second transistor being enabled or disabled responsive to the output of said first logic element.

Claim 34

A circuit for defining a logic state in an integrated circuit, comprising: a first logic element having an input and an output; a fuse element having a first terminal and a second terminal wherein the first terminal is coupled to the input of said first logic element, said fuse element being selectively configured in a conducting or a non-conducting state between said first and second terminals; circuitry for receiving a logic signal at said first terminal; a first transistor having a control electrode and having a conduction path coupled between a first voltage source and the input of said first logic element, said conduction path of said first transistor being enabled or disabled responsive to the output of said first logic element; and a second transistor having a control electrode and having a conduction path coupled between the second terminal of said fuse element and a second voltage source such that said second voltage source is decoupled from said input of said first logic element if said fuse element is in said non-conductive state, said conduction path of said second transistor being enabled or disabled responsive to the output of said first logic element.