US5280201A
Expired / Lapsed
US
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Semiconductor logic circuit apparatus
Assignee: Renesas Electronics Corp
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Filing: 1991-09-17
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Granted: 1994-01-18
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Expires: 2011-09-17
Abstract
Abstract A semiconductor logic circuit apparatus which include a first switching element consisting of a field effect transistor for changing holding data, an inverter circuit whose input is connected with one end of the first switching element, a feedback circuit whose input and output are connected with the output and input of the inverter circuit, and a second switching element connected between the output of the feedback circuit and first or second potential. The second switching element is effective for enabling and disabling the feedback circuit. The first and second switching elements are opened/closed in reverse phase to each other. Feedback of the feedback circuit is prevented until the inverter circuit is driven from its "0" to its "1" holding state, so that driving of the inverter circuit becomes easy and operational stability and operating speed are enhanced.
Inventors
- 👤 Kumiko Fujimori
- 👤 Hirofumi Shinohara
- 👤 Noriaki Matsumoto
- 👤 Shuichi Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:21
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356165; H03K3/356113; H03K3/356147
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
185 words
A semiconductor logic circuit apparatus for holding data, comprising: first switching means, which includes a plurality of conductive type field effect transistors whose one ends are commonly connected, for changing said holding data; an inverter circuit, receiving an input from commonly connected one ends of said first switching means and producing an output; a feedback circuit, disposed between a first potential and a second potential; an input node of said feedback circuit being connected to an output node of said inverter circuit; an output node of said feedback circuit being connected to an input node of said inverter circuit; means for supplying a data input to said first switching means; and second switching means, coupled between an output of said feedback circuit and one of said first potential and said second potential; and said second switching means being responsive to a second control signal such that said feedback circuit is enabled when all of said first switching means are non-conductive in response to a first control signal, and such that said feedback circuit is disabled when any one of said first switching means is conductive.
Claim 2
Dependent Claim
185 words
A semiconductor logic circuit apparatus for holding data, comprising: first switching means, which includes a plurality of conductive type field effect transistors whose one ends are commonly connected, for changing said holding data; an inverter circuit, receiving an input from commonly connected one ends of said first switching means and producing an output; a feedback circuit, disposed between a first potential and a second potential; an input node of said feedback circuit being connected to an output node of said inverter circuit; an output node of said feedback circuit being connected to an input node of said inverter circuit; means for supplying a data input to said first switching means; and second switching means, coupled between an output of said feedback circuit and one of said first potential and said second potential; and said second switching means being responsive to a second control signal such that said feedback circuit is enabled when all of said first switching means are non-conductive in response to a first control signal, and such that said feedback circuit is disabled when any one of said first switching means is conductive.
Claim 3
Dependent Claim
231 words
A semiconductor logic circuit apparatus for holding data, comprising: a plurality of input nodes each receiving an input data; a control signal generating means for generating a plurality of first control signals; a plurality of first switching transistors each having a first main electrode, a second main electrode, and a control terminal; said first main electrode being connected to a respective one of said input nodes; said second main electrode being connected to a common node; and said control electrode receiving the corresponding first control signal; an inverter circuit having an input node connected to said common node, and an output node for outputting an output data; a feedback circuit having a P-channel type transistor and an N-channel type transistor; said P-channel type transistor being connected between a supply potential node and said common node; said N-channel type transistor being connected between a ground potential node and said common node; and control electrodes of said P-channel and N-channel type transistors being connected to the output node of said inverter circuit; a second switching transistor connected in series with said P-channel and N-channel type transistors; and said second switching transistor being responsive to a second control signal such that said second switching transistor is conductive when all of said first switching transistors are non-conductive and such that said second switching transistor is non-conductive when one of said first switching transistor is conductive.
Claim 4
Dependent Claim
231 words
A semiconductor logic circuit apparatus for holding data, comprising: a plurality of input nodes each receiving an input data; a control signal generating means for generating a plurality of first control signals; a plurality of first switching transistors each having a first main electrode, a second main electrode, and a control terminal; said first main electrode being connected to a respective one of said input nodes; said second main electrode being connected to a common node; and said control electrode receiving the corresponding first control signal; an inverter circuit having an input node connected to said common node, and an output node for outputting an output data; a feedback circuit having a P-channel type transistor and an N-channel type transistor; said P-channel type transistor being connected between a supply potential node and said common node; said N-channel type transistor being connected between a ground potential node and said common node; and control electrodes of said P-channel and N-channel type transistors being connected to the output node of said inverter circuit; a second switching transistor connected in series with said P-channel and N-channel type transistors; and said second switching transistor being responsive to a second control signal such that said second switching transistor is conductive when all of said first switching transistors are non-conductive and such that said second switching transistor is non-conductive when one of said first switching transistor is conductive.
Claim 5
Dependent Claim
44 words
A semiconductor logic circuit apparatus according to claim 2 comprising a control signal generating means responsive to said second control signal for generating said first control signals such that all of said first switching transistors are non-conductive when said second switching transistor is conductive.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |