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US5490257A
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RAM based FIFO memory half-full detection apparatus and method
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-02-24
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Granted: 1996-02-06
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Expires: 2012-02-24
Abstract
Abstract A method for detecting a half-full condition of a first-in, first-out memory array. The method of the invention includes the steps of a) moving a write pointer through the array to write data to alternating rows of the memory array; b) moving a read pointer through the array to read data from the alternating rows of the memory array in first-in, first-out order; and c) providing a half-full indication when the read pointer and the write pointer point to adjacent rows in the memory array. This method eliminates the need to route lines across the array to detect a half-full condition, thereby reducing die and power requirements and offering an increase in speed.
Inventors
- 👤 Barry A. Hoberman
- 👤 Stuart T. Auvinen
- 👤 Patrick Wang
- 👤 David Wang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 08:20
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/10; G06F5/12; G06F2205/00; G06F2205/12; G06F2205/126
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
144 words
A system for detecting a half-full condition of a memory array having N×M memory cells, where N is the number of rows in the array and M is the number of columns, said half-full detection system comprising: write row pointing means for providing a write control pointer to alternating rows of said memory array; read row pointing means for providing a read control pointer to alternating rows of said memory array; and detection logic means for detecting a read control pointer on one row of said memory array and a write control pointer on an adjacent row of said memory array, said detection logic means further including N AND gates, each gate having a read control pointer from one row, row n, where n=1 to N, as one input and a write control pointer on an adjacent row, row n+1 as a second input.
Claim 2
Independent Claim
144 words
A system for detecting a half-full condition of a memory array having N×M memory cells, where N is the number of rows in the array and M is the number of columns, said half-full detection system comprising: write row pointing means for providing a write control pointer to alternating rows of said memory array; read row pointing means for providing a read control pointer to alternating rows of said memory array; and detection logic means for detecting a read control pointer on one row of said memory array and a write control pointer on an adjacent row of said memory array, said detection logic means further including N AND gates, each gate having a read control pointer from one row, row n, where n=1 to N, as one input and a write control pointer on an adjacent row, row n+1 as a second input.
Claim 3
Dependent Claim
27 words
The invention of claim 1 wherein said detection logic means includes an OR gate and the outputs of said AND gates are provided as the inputs thereof.
Claim 4
Independent Claim
144 words
A system for detecting a half-full condition of a memory array having N×M memory cells, where N is the number of rows in the array and M is the number of columns, said half-full detection system comprising: write column pointing means for providing a write control pointer to alternating columns of said memory array; read column pointing means for providing a read control pointer to alternating columns of said memory array; and detection logic means for detecting a read control pointer on one column of said memory array and a write control pointer on an adjacent column of said memory array, said detection logic means further including M AND gates, each gate having a read control pointer from one column, column m, where m=1 to M, as one input and a write control pointer on an adjacent column, column n+1 as a second input.
Claim 5
Independent Claim
144 words
A system for detecting a half-full condition of a memory array having N×M memory cells, where N is the number of rows in the array and M is the number of columns, said half-full detection system comprising: write column pointing means for providing a write control pointer to alternating columns of said memory array; read column pointing means for providing a read control pointer to alternating columns of said memory array; and detection logic means for detecting a read control pointer on one column of said memory array and a write control pointer on an adjacent column of said memory array, said detection logic means further including M AND gates, each gate having a read control pointer from one column, column m, where m=1 to M, as one input and a write control pointer on an adjacent column, column n+1 as a second input.
Claim 6
Dependent Claim
27 words
The invention of claim 3 wherein said detection logic means includes an OR gate and the outputs of said AND gates are provided as the inputs thereof.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-02-05 | 1999-08-07 | 2000-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-02-05 | 2003-08-07 | 2004-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-02-05 | 2007-08-07 | 2008-02-06 | $7700.00 | Window Closed / Lapsed |