US4875196A
Expired / Lapsed
US
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Method of operating data buffer apparatus
Assignee: Sharp Microelectronics Technology Inc
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Filing: 1987-09-08
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Granted: 1989-10-17
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Expires: 2007-09-08
Abstract
Abstract An improved First-In, First-Out data buffer and method of operation incorporates a plurality of arrays of random-access memory cells in column and row orientation per array in which all the cells in a row of one array are precharged simultaneously as memory cells are accessed for read or write operations in another array. Also, all the cells in a row of the other array may be precharged as the memory cells in the one array are accessed independently for read or write operations. Accesses to memory cells in addressed rows alternate from one array to another so that the signal conditioning of the memory cells in one array can take place before access in needed and while memory cells are being accessed in another array. Improved status logic unambigously designates the conditions of empty, half full and full, independent of the sequence of data read and write operations. Data signal driver circuitry controls the rate of change of data output signals for improved noise performance and compatibility with external circuitry.
Inventors
- 👤 Dieter W. Spaderna
- 👤 Jeffrey L. Miller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:13
CPC Classifications
G; G06; G06F; G06F5/00; G06F5/06; G06F5/16; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C7/1051; G11C7/106; G11C8/00; G11C8/16
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
579 words
A method of operating a plurality of arrays for dual-ported randomly-accessable memory cells having read and write word lines and read and write bit lines per memory cell to which a data signal is written and from which a data signal is read by precharging of bit lines during an interval, and in response to control signal applied to a word line thereof during another interval, where the memory cells have the associated write word lines and the read word lines arranged in consecutive rows and have the associated read bit lines and the write bit lines arranged in columns in each array, the method comprising the steps of: applying wirte word line control signals to all of the memory cells arranged in a selected row in one of the arrays during one write interval; precharging during said one write interval the write bit lines of the memory cells arranged in another of the arrays while control signal for said write word llines is absent from all of the memory cells in said another array; writing data signals to the memory cells arranged in selected columns within said one array along the selected row by accessing a number of the columns of memory cells in said one array during said one write interval for writing data signal therein; applying write word line control signals to all of the memory cells arranged in a selected row in said another of the arrays during another write interval; precharging during said another write interval the write bit lines of the memory cells arranged in said one of the arrays while control signal for the write word lines is absent from all of the memory cells in said one of the arrays; writing data signals to the memory cells arranged in selected columns within said another array along the selected row by accessing a number of the columns of memory cells in said another array during said another write interval for writing data signals therein; applying read word line control signals to all of the memory cells arranged in a selected row in said one of the arrays during one read interval that is independent of said one and said another write intervals; precharging during said one read interval the read bit lines of the memory cells arranged in another of the arrays while control signal for said read word lines is absent from all of the memory cells in said another array; reading data signals from the memory cells arranged in selected columns within said one array along the selected row by accessing a number of the columns of memory cells in said one array during said one read interval for reading data signals therein; applying said read word line control signals to all of the memory cells arranged in a selected row in said another of the arrays during another read interval that is independent of said one and said another write intervals; precharging during said another read interval the read bit lines of the memory cells arranged in said one of the arrays while control signal for said read word lines is absent from all of the memory cells in said one of the arrays; and reading data signals from the memory cells arranged in selected columns within said another array along the selected row by accessing a number of the columns of memory cells in said another array during said another read interval for reading the data signals therein.
Claim 2
Independent Claim
579 words
A method of operating a plurality of arrays for dual-ported randomly-accessable memory cells having read and write word lines and read and write bit lines per memory cell to which a data signal is written and from which a data signal is read by precharging of bit lines during an interval, and in response to control signal applied to a word line thereof during another interval, where the memory cells have the associated write word lines and the read word lines arranged in consecutive rows and have the associated read bit lines and the write bit lines arranged in columns in each array, the method comprising the steps of: applying wirte word line control signals to all of the memory cells arranged in a selected row in one of the arrays during one write interval; precharging during said one write interval the write bit lines of the memory cells arranged in another of the arrays while control signal for said write word llines is absent from all of the memory cells in said another array; writing data signals to the memory cells arranged in selected columns within said one array along the selected row by accessing a number of the columns of memory cells in said one array during said one write interval for writing data signal therein; applying write word line control signals to all of the memory cells arranged in a selected row in said another of the arrays during another write interval; precharging during said another write interval the write bit lines of the memory cells arranged in said one of the arrays while control signal for the write word lines is absent from all of the memory cells in said one of the arrays; writing data signals to the memory cells arranged in selected columns within said another array along the selected row by accessing a number of the columns of memory cells in said another array during said another write interval for writing data signals therein; applying read word line control signals to all of the memory cells arranged in a selected row in said one of the arrays during one read interval that is independent of said one and said another write intervals; precharging during said one read interval the read bit lines of the memory cells arranged in another of the arrays while control signal for said read word lines is absent from all of the memory cells in said another array; reading data signals from the memory cells arranged in selected columns within said one array along the selected row by accessing a number of the columns of memory cells in said one array during said one read interval for reading data signals therein; applying said read word line control signals to all of the memory cells arranged in a selected row in said another of the arrays during another read interval that is independent of said one and said another write intervals; precharging during said another read interval the read bit lines of the memory cells arranged in said one of the arrays while control signal for said read word lines is absent from all of the memory cells in said one of the arrays; and reading data signals from the memory cells arranged in selected columns within said another array along the selected row by accessing a number of the columns of memory cells in said another array during said another read interval for reading the data signals therein.
Claim 3
Dependent Claim
47 words
The method according to claim 1 wherein a control signal is applied to the read word line of a selected row of memory cells in an array for the duration of a plural number of consecutive read data access intervals for memory cells along the selected row.
Claim 4
Dependent Claim
47 words
The method according to claim 1 wherein a control signal is applied to the write word line of a selected row of memory cells in an array for the duration of a plural number of consecutive write data access intervals for memory cells along the selected row.
Claim 5
Dependent Claim
54 words
The method according to claim 1 comprising the steps of: detecting the reading and the writing of data signals substantially simultaneously from memory cells along a selected row in an array; and in response thereto, connecting the read bit lines to the corresponding write bit lines of each memory cell along the selected row.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-16 | 1993-04-17 | 1993-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-16 | 1997-04-17 | 1997-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-16 | 2001-04-17 | 2001-10-17 | $7700.00 | Window Closed / Lapsed |