Memory cell for sequentially addressed memory array

Claim 3

The method of addressing according to claim 1 and further including precharging said read/write means immediately prior to each of said steps of addressing.

Claim 4

The method according to claim 2 wherein a sequence of steps consisting of precharging the read/write lines, addressing a column of read terminals, precharging the read/write lines, and addressing the write enable columns, comprises one state time and said step of addressing one column of read enable terminals includes the steps of: a. delaying said information one and one-half state time; and thereafter b. impressing said information onto said read/write means to thereby recirculate said information.

Claim 5

The method according to claim 2 wherein a sequency of steps consisting of precharging the read/write lines, addressing a column of read terminals, precharging the read/write lines, and addressing the write enable columns, comprises one state time and said step of addressing one column of read enable terminals includes: a. delaying said information one and one-half state times; and thereafter b. impressing said information onto said read/write means to thereby right shift said information.

Claim 6

In a memory system: a plurality of identical memory cells arranged in an array of rows and columns; each memory cell comprising a data input terminal, a data output terminal, capacitive data storing means, a reference potential source, and first, second and third switching devices each having an output cirCuit and a control terminal, the output circuits of the first and second switching devices being connected in series between said potential source and the data output terminal, the capacitive data storing means being connected between the potential source and the control terminal of the first switching device, the output circuit of the third switching device being connected between the data input terminal and the control terminal of the first switching device, the data input terminal and data output terminal being directly connected together and coupled to data input/output means; means connecting the data input/output means of each separate row of the cells in common; first address means connecting the control terminals of all of the second switching devices of each separate column of cells in common; second address means connecting the control terminals of all of the third switching devices of each separate column in common; and means for actuating the first and second address means in an ordered sequence wherein the columns are addressed in overlapping manner by actuating the second address means of a given column, then actuating the first address means of the preceding column, then actuating the second address means of the succeeding column, then actuating the first address means of said given column.

Claim 7

In a memory system: a plurality of identical memory cells arranged in an array of rows and columns; each memory cell comprising a data input terminal, a data output terminal, capacitive data storing means, a reference potential source, and first, second and third switching devices each having an output cirCuit and a control terminal, the output circuits of the first and second switching devices being connected in series between said potential source and the data output terminal, the capacitive data storing means being connected between the potential source and the control terminal of the first switching device, the output circuit of the third switching device being connected between the data input terminal and the control terminal of the first switching device, the data input terminal and data output terminal being directly connected together and coupled to data input/output means; means connecting the data input/output means of each separate row of the cells in common; first address means connecting the control terminals of all of the second switching devices of each separate column of cells in common; second address means connecting the control terminals of all of the third switching devices of each separate column in common; and means for actuating the first and second address means in an ordered sequence wherein the columns are addressed in overlapping manner by actuating the second address means of a given column, then actuating the first address means of the preceding column, then actuating the second address means of the succeeding column, then actuating the first address means of said given column.

Claim 8

A memory system according to claim 5 wherein the means for actuating the address means functions to actuate only one of the address means on only one column in the array at any given time.

Claim 9

A memory system according to claim 5 wherein the first, second and third switching devices are MOS transistors, wherein the array is in the form of an integrated semiconductor chip, wherein the data input and data output terminals are connected together by elongated regions of semiconductor material in the semiconductor chip, and wherein the first and second address means comprises metal film strips on the semiconductor chip.

Claim 10

A memory system according to claim 7 and including left shift and right shift delay means provided on the chip for coupling the data input and data output terminals of each row to provide time delayed reinsertion of bits read out of a given cell.

Claim 11

A selectively addressable memory system comprising: a. a random access memory array having rows and columns of selectively addressable memory cells having read, write, read enable, and write enable terminals with all read enable terminals in a respective column commonly coupled, and all write enable terminals in a respective column commonly coupled, all read terminals in a respective row commonly coupled, and all write terminals in a respective row commonly coupled; b. means commonly coupling said read and write terminals for selectively conveying input and output data to and from said cells; and c. commutator means for cyclically addressing individual columns in an ordered bidirectional sequence.

Claim 12

A selectively addressable memory system comprising: a. a random access memory array having rows and columns of selectively addressable memory cells having read, write, read enable, and write enable terminals with all read enable terminals in a respective column commonly coupled, and all write enable terminals in a respective column commonly coupled, all read terminals in a respective row commonly coupled, and all write terminals in a respective row commonly coupled; b. means commonly coupling said read and write terminals for selectively conveying input and output data to and from said cells; and c. commutator means for cyclically addressing individual columns in an ordered bidirectional sequence.

Claim 13

The memory system of claim 9 wherein said commutator means includes means for periodically addressing, in sequence, read enable terminals of one column, write enable terminals of one adjacent column, and read enable terminals of the other adjacent column and write enable terminals of said one column, respectively.

Claim 14

The memory system of claim 9 wherein said input and output data means commonly connects said read and said write terminals.

Claim 15

The memory system of claim 11 wherein said commutator means includes: a. a multiphase signal generator providing a multi-phase signal, said phase representing a state time; and b. logic means responsive to said signal generator for selectively addressing columns of said read and write enable terminals individually and alternately.

Claim 16

The memory system of claim 12 wherein said signal generator provides said multi-phase signal having phases equal in number to the number of said columns, wherein each of said phases consists of a logic one signal interval and a logic zero signal interval and said logic one leVel represents a state time.

Claim 17

The memory system of claim 13 wherein said first plurality of phased clock signals comprises two signals, occurring in a period of one state time.

Claim 18

The memory system of claim 12 wherein said logic means is further responsive to a first plurality of phased clock signals.

Claim 19

The memory system of claim 15 and further including means responsive to a second plurality of phased clock signals for selectively precharging said read and write means.

Claim 20

The memory system of claim 16 and further including recirculate means comprising a signal delay means of one and one-half state times responsive to one of said second plurality of clock signals for rewriting said output data into the respective cells from which it was read.

Claim 21

The memory system of claim 17 and further including right shift means responsive to one of said second plurality of phased clock signals for right shifting said output signals from one column into the adjacent column.

Claim 22

The memory system of claim 18 wherein said right shift means comprises a signal delay means of one-half state time.