Analog current mode analog/digital converter

Claim 2

An analog to digital converter for converting an analog input voltage signal to a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first pair of differential input transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal to produce a first analog difference signal; a second digital to analog converter for converting a second plurality of bits to a second analog voltage signal; and a second pair of differential input transistors having a pair of inputs coupled to the second analog voltage signal and a reference voltage signal to produce a second analog difference signal; a coupler circuit for coupling the first and second analog difference signals to produce an analog residual signal; and a residual converter for converting the residual analog signal to a digital representation.

Claim 3

The converter of claim 1 wherein each transistor of the pairs of differential input transistors are MOS transistors and the channel width of transistors of the second pair is scaled relative to the channel width of the first pair.

Claim 4

The converter of claim 1 wherein the transistors are MOS transistors and each pair of differential input transistors has a single MOS transistor current source providing current to the associated pair.

Claim 5

The converter of claim 3 wherein each transistor of the pairs of differential input transistors and associated current sources has the same channel length.

Claim 6

The converter of claim 3 wherein the channel width of the transistors of the second pair and its associated same channel length current source is scaled relative to the channel width of the transistors of the first pair and its associated same channel length current source.

Claim 7

An analog to digital converter for converting an analog input voltage signal to a digital representation of h bits, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal, said first converter comprising a string k of resistors connected in series, wherein k is less than 2 h ; a first pair of differential input MOS transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal, respectively, to produce a first analog difference signal; a second digital to analog converter for converting a second plurality of bits to a second analog voltage signal, said second converter comprising at least a portion of the string of series-connected resistors of the first converter; and a second pair of differential input MOS transistors having a pair of inputs coupled to the second analog voltage signal and a tap point of the string of series-connected resistors of the first converter, respectively, to produce a second analog difference signal, said second pair of differential input transistors being scaled in size relative to the first pair of differential input transistors so that the second pair has a transconductance g m which is a fraction of the transconductance of the first pair; a coupler circuit for coupling the first and second analog difference signals to produce an analog residual signal; and a residual converter for converting the residual analog signal to a digital representation.

Claim 8

An analog to digital converter for converting an analog input voltage signal to a digital representation of h bits, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal, said first converter comprising a string k of resistors connected in series, wherein k is less than 2 h ; a first pair of differential input MOS transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal, respectively, to produce a first analog difference signal; a second digital to analog converter for converting a second plurality of bits to a second analog voltage signal, said second converter comprising at least a portion of the string of series-connected resistors of the first converter; and a second pair of differential input MOS transistors having a pair of inputs coupled to the second analog voltage signal and a tap point of the string of series-connected resistors of the first converter, respectively, to produce a second analog difference signal, said second pair of differential input transistors being scaled in size relative to the first pair of differential input transistors so that the second pair has a transconductance g m which is a fraction of the transconductance of the first pair; a coupler circuit for coupling the first and second analog difference signals to produce an analog residual signal; and a residual converter for converting the residual analog signal to a digital representation.

Claim 9

The converter of claim 6 wherein the transconductance g m of the second pair is a fraction 1/n, wherein n is an integer, of the transconductance of the first pair.

Claim 10

The converter of claim 6 wherein the first plurality of bits equals j bits and the string of k resistors does not exceed 2 j resistors.

Claim 11

The converter of claim 8 wherein the transconductance g m of the second pair is a fraction 2 j /2 h of the transconductance of the first pair.

Claim 12

The converter of claim 6 wherein the first plurality of bits equals j bits and the string of k resistors exceeds 2 j resistors.

Claim 13

An analog to digital converter for converting an analog input voltage signal to a digital representation, comprising: a first analog to digital converter for converting a first portion of the analog input signal to a first plurality of bits and a second plurality of bits; a first digital to analog converter for converting the first plurality of bits to a first analog voltage signal; a first transconductance circuit for providing a first current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal; a second transconductance circuit for providing a second current signal which is a function of the second analog voltage signal; an output node for providing a residual current signal which is a function of the difference between the first and second current signals; and a residual converter for converting the residual current signal to a digital representation.

Claim 14

An analog to digital converter for converting an analog input voltage signal to a digital representation, comprising: a first analog to digital converter for converting a first portion of the analog input signal to a first plurality of bits and a second plurality of bits; a first digital to analog converter for converting the first plurality of bits to a first analog voltage signal; a first transconductance circuit for providing a first current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal; a second transconductance circuit for providing a second current signal which is a function of the second analog voltage signal; an output node for providing a residual current signal which is a function of the difference between the first and second current signals; and a residual converter for converting the residual current signal to a digital representation.

Claim 15

A subranging circuit for an analog to digital converter for converting an analog input voltage signal to a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first transconductance circuit for providing a first current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal; a second transconductance circuit for providing a second current signal which is a function of the second analog voltage signal; and an output node for providing a residual current signal which is a function of the difference between the first and second current signals.

Claim 16

A subranging circuit for an analog to digital converter for converting an analog input voltage signal to a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first transconductance circuit for providing a first current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal; a second transconductance circuit for providing a second current signal which is a function of the second analog voltage signal; and an output node for providing a residual current signal which is a function of the difference between the first and second current signals.

Claim 17

The subranging circuit of claim 12 further comprising a transimpedance stage for converting the residual current signal to a residual voltage signal.

Claim 18

A comparator for comparing an analog input voltage signal to the analog of a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first transconductance circuit for providing a first current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal; a second transconductance circuit for providing a second current signal which is a function of the second analog voltage signal; an output node for providing a residual current signal which is a function of the difference between the first and second current signals; and a latch for latching a digital value as a function of the residual current signal.

Claim 19

A comparator for comparing an analog input voltage signal to the analog of a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first transconductance circuit for providing a first current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal; a second transconductance circuit for providing a second current signal which is a function of the second analog voltage signal; an output node for providing a residual current signal which is a function of the difference between the first and second current signals; and a latch for latching a digital value as a function of the residual current signal.

Claim 20

A circuit for processing an analog input voltage signal and a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first pair of differential input transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal to produce a first analog current signal; a second digital to analog converter for converting a second plurality of bits to a second analog voltage signal; and a second pair of differential input transistors having a pair of inputs coupled to the second analog voltage signal and a reference voltage signal to produce a second analog current signal; an output circuit for providing an output signal which is a function of the difference between the first and second analog current signals.

Claim 21

A circuit for processing an analog input voltage signal and a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal; a first pair of differential input transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal to produce a first analog current signal; a second digital to analog converter for converting a second plurality of bits to a second analog voltage signal; and a second pair of differential input transistors having a pair of inputs coupled to the second analog voltage signal and a reference voltage signal to produce a second analog current signal; an output circuit for providing an output signal which is a function of the difference between the first and second analog current signals.

Claim 22

The circuit of claim 15 wherein each transistor of the pairs of differential input transistors are MOS transistors and the channel width of transistors of the second pair is scaled relative to the channel width of the first pair.

Claim 23

The circuit of claim 15 wherein each transistor of the pairs of differential input transistors is a MOS transistor and each pair of differential input transistors has a single MOS transistor current source providing current to the associated pair.

Claim 24

The circuit of claim 17 wherein each transistor of the pairs of differential input transistors and associated current sources has the same channel length.

Claim 25

The circuit of claim 17 wherein the channel width of the transistors of the second pair and its associated same channel length current source is scaled relative to the channel width of the transistors of the first pair and its associated same channel length current

Claim 26

A comparator for comparing an analog input signal to a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog signal; a first pair of differential input transistors having a pair of inputs coupled to the first analog signal and the analog input signal to produce a first analog difference signal; a second digital to analog converter for converting a second plurality of bits to a second analog signal; and a second pair of differential input transistors having a pair of inputs coupled to the second analog signal and a reference signal to produce a second analog difference signal; a coupler circuit for coupling the first and second analog difference signals to produce an analog residual signal; and a latch that latches to a digital value as a function of the residual signal.

Claim 27

A comparator for comparing an analog input signal to a digital representation, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog signal; a first pair of differential input transistors having a pair of inputs coupled to the first analog signal and the analog input signal to produce a first analog difference signal; a second digital to analog converter for converting a second plurality of bits to a second analog signal; and a second pair of differential input transistors having a pair of inputs coupled to the second analog signal and a reference signal to produce a second analog difference signal; a coupler circuit for coupling the first and second analog difference signals to produce an analog residual signal; and a latch that latches to a digital value as a function of the residual signal.

Claim 28

The comparator of claim 20 wherein each transistor of the pairs of differential input transistors are MOS transistors and the channel width of transistors of the second pair is scaled relative to the channel width of the first pair.

Claim 29

The comparator of claim 20 wherein each transistor is a MOS transistor and each pair of differential input MOS transistors has a single transistor current source providing current to the associated pair.

Claim 30

The comparator of claim 22 wherein each transistor of the pairs of differential input transistors and associated current sources has the same channel length.

Claim 31

The comparator of claim 23 wherein the channel width of the transistors of the second pair and its associated same channel length current source is scaled relative to the channel width of the transistors of the first pair and its associated same channel length current source.

Claim 32

An analog to digital converter for converting an analog input voltage signal to a digital representation of h bits, comprising: a first analog to digital converter for converting a portion of the analog input voltage signal to a digital representation comprising first and second pluralities of bits; a first digital to analog converter for converting the first plurality of bits to a first analog voltage signal, said first converter comprising a string k of resistors connected in series, wherein k is less than 2 h ; a first pair of differential input MOS transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal, respectively, to produce a first analog current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal, said second converter comprising at least a portion of the string of series-connected resistors of the first converter; and a second pair of differential input MOS transistors having a pair of inputs coupled to the second analog voltage signal and a tap point of the string of series-connected resistors of the first converter, respectively, to produce a second analog current signal which is a function of the second analog input signal, said second pair of differential input MOS transistors being scaled in transconductance relative to the first pair of differential input transistors so that the second pair has a transconductance g m which is a fraction of the transconductance of the first pair; a transimpedance stage coupled to the outputs of the first and second pairs of differential input MOS transistors to provide a residual voltage signal which is a function of the difference between the first and second analog current signals; and a residual converter for converting the residual analog voltage signal to a digital representation.

Claim 33

An analog to digital converter for converting an analog input voltage signal to a digital representation of h bits, comprising: a first analog to digital converter for converting a portion of the analog input voltage signal to a digital representation comprising first and second pluralities of bits; a first digital to analog converter for converting the first plurality of bits to a first analog voltage signal, said first converter comprising a string k of resistors connected in series, wherein k is less than 2 h ; a first pair of differential input MOS transistors having a pair of inputs coupled to the first analog voltage signal and the analog input voltage signal, respectively, to produce a first analog current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal, said second converter comprising at least a portion of the string of series-connected resistors of the first converter; and a second pair of differential input MOS transistors having a pair of inputs coupled to the second analog voltage signal and a tap point of the string of series-connected resistors of the first converter, respectively, to produce a second analog current signal which is a function of the second analog input signal, said second pair of differential input MOS transistors being scaled in transconductance relative to the first pair of differential input transistors so that the second pair has a transconductance g m which is a fraction of the transconductance of the first pair; a transimpedance stage coupled to the outputs of the first and second pairs of differential input MOS transistors to provide a residual voltage signal which is a function of the difference between the first and second analog current signals; and a residual converter for converting the residual analog voltage signal to a digital representation.

Claim 34

A processing circuit for processing an analog input voltage signal and a digital representation of h bits or more, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal, said first converter comprising a string k of resistors connected in series, wherein k is less than 2 h ; a first pair of differential input transistors having a pair of inputs coupled to the first analog signal and the analog input signal, respectively, to produce a first analog current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal, said second converter comprising at least a portion of the string of series-connected resistors of the first converter; and a second pair of differential input transistors having a pair of inputs coupled to the second analog voltage signal and a tap point of the string of series-connected resistors of the first converter, respectively, to produce a second analog current signal which is a function of the second analog voltage signal, said second pair of differential input transistors being scaled in transconductance relative to the first pair of differential input transistors so that the second pair has a transconductance g m which is a fraction of the transconductance of the first pair.

Claim 35

A processing circuit for processing an analog input voltage signal and a digital representation of h bits or more, comprising: a first digital to analog converter for converting a first plurality of bits to a first analog voltage signal, said first converter comprising a string k of resistors connected in series, wherein k is less than 2 h ; a first pair of differential input transistors having a pair of inputs coupled to the first analog signal and the analog input signal, respectively, to produce a first analog current signal which is a function of the difference between the first analog voltage signal and the analog input voltage signal; a second digital to analog converter for converting the second plurality of bits to a second analog voltage signal, said second converter comprising at least a portion of the string of series-connected resistors of the first converter; and a second pair of differential input transistors having a pair of inputs coupled to the second analog voltage signal and a tap point of the string of series-connected resistors of the first converter, respectively, to produce a second analog current signal which is a function of the second analog voltage signal, said second pair of differential input transistors being scaled in transconductance relative to the first pair of differential input transistors so that the second pair has a transconductance g m which is a fraction of the transconductance of the first pair.

Claim 36

The processing circuit of claim 26 further comprising: a transimpedance stage coupled to the outputs of the first and second pairs of differential input transistors to provide a residual voltage signal which is a function of the difference between the first and second analog current signals; and a latch for providing a digital output as a function of the residual voltage signal.

Claim 37

The circuit of claim 26 wherein the transconductance g m of the second pair is a fraction 1/n, wherein n is an integer, of the transconductance of the first pair.

Claim 38

The circuit of claim 26 wherein the first plurality of bits equals j bits and the string of k resistors does not exceed 2 j resistors.

Claim 39

The circuit of claim 29 wherein the transconductance g m of the second pair is a fraction 2 j /2 h of the transconductance of the first pair.

Claim 40

The circuit of claim 26 wherein the first plurality of bits equals j bits and the string of k resistors exceeds 2 j resistors.

Claim 41

The circuit of claim 26 wherein the transistors are MOS transistors.