US5117235A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Feedback comparison type analog-to-digital converter
Assignee: Samsung Electronics Co Ltd
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Filing: 1990-02-01
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Granted: 1992-05-26
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Expires: 2010-02-01
Abstract
Abstract An analog-to-digital converter comprises plural amplifiers, a first group of transistors for input, a second group of transistor for biasing, a third group of transistors for feedback and plural inverters. The first group of transistors are PMOS transistors, and the second and third groups of transistors are NMOS transistors. The connecting weight of each transistor may be set with the conductance values thereof in accordance with a geometrical aspect ratio W/L of MOS transistors. The amplifiers comprise two CMOS inverters connected in series.
Inventors
- 👤 Jeong Ho-sun
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:52
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/34; H03M1/38; H03M1/42
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
189 words
An analog to digital converter which converts analog signals into Nbit digital signals comprising; a plurality of amplifiers corresponding to each bit of said digital signals, each of said amplifiers having a corresponding input line; a first group of transistors for connecting a first power source in common with each said input line of said amplifiers, having a connecting weight in accordance with a level change of said analog signals; a second group of transistors for connecting a second power source in common with each said input line of said amplifiers, said second group of transistors having connecting weights with weighting values of each bit of Nbits when applying said first power source; a third group of transistors for selectively connecting said second power source in common with each said input line of the amplifiers corresponding to lower order bits in accordance with output values output from the amplifiers corresponding to higher order bits, said third group of transistors having connecting weights with weighting values indicative of the output of the amplifiers corresponding to the higher order bits; a plurality of inverters for inverting each output of said amplifiers.
Claim 2
Dependent Claim
189 words
An analog to digital converter which converts analog signals into Nbit digital signals comprising; a plurality of amplifiers corresponding to each bit of said digital signals, each of said amplifiers having a corresponding input line; a first group of transistors for connecting a first power source in common with each said input line of said amplifiers, having a connecting weight in accordance with a level change of said analog signals; a second group of transistors for connecting a second power source in common with each said input line of said amplifiers, said second group of transistors having connecting weights with weighting values of each bit of Nbits when applying said first power source; a third group of transistors for selectively connecting said second power source in common with each said input line of the amplifiers corresponding to lower order bits in accordance with output values output from the amplifiers corresponding to higher order bits, said third group of transistors having connecting weights with weighting values indicative of the output of the amplifiers corresponding to the higher order bits; a plurality of inverters for inverting each output of said amplifiers.
Claim 3
Dependent Claim
29 words
An analog to digital converter according to claim 1, wherein said first group of transistors are PMOS transistors and said second and third groups of transistors are NMOS transistors.
Claim 4
Dependent Claim
23 words
An analog to digital converter according to claim 2, wherein said connecting weight of each said transistor corresponds to a conductance value thereof.
Claim 5
Dependent Claim
25 words
An analog to digital converter according to claim 3, wherein said conductance value of each said transistor is set with a geometrical aspect ratio W/L.
Claim 6
Dependent Claim
20 words
An analog to digital converter according to claim 1, wherein each said amplifier comprises two CMOS inverters connected in series.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-05-26 | 1995-11-25 | 1996-05-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-05-26 | 1999-11-25 | 2000-05-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-05-26 | 2003-11-25 | 2004-05-26 | $7700.00 | Window Closed / Lapsed |