Patent US5487153A successfully refreshed from Google Patents.
US5487153A
Expired / Lapsed
US
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Neural network sequencer and interface apparatus
Assignee: Adaptive Solutions Inc
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Filing: 1994-06-24
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Granted: 1996-01-23
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Expires: 2014-06-24
Abstract
Abstract The sequencer (14) is part of a computational system (10) which includes a computational circuit component, or processor node array (16); the sequencer, or controller component (14); and a boundary interface (34) between the computational circuit component (16) and the controller component (14). The controller component (14) provides three main functions in the system: (one) it sequences computations in a computational component (16), which includes an array of processor nodes (74, 76, 78, 80, 82, 84); (two) it provides I/O processing (20) from several disparate sources between the processor node array (16) and a host processor (12); and (three) it synchronizes data flow from a substantially asynchronous portion of the system (12) with a substantially synchronous data flow in the processor node array portion of the system (16).
Inventors
- 👤 Daniel W. Hammerstrom
- 👤 Dean W. Mueller
- 👤 Stephen G. Owens
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 07:52
CPC Classifications
G; G06; G06N; G06N3/00; G06N3/02; G06N3/10; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 37
Claim 1
Independent Claim
92 words
A computational system (10) for use with a host processor (12) having a memory unit (12a) therein, comprising: at least one single-instruction multiple-data (SIMD) computational circuit component (16) having a first timing characteristic for processing inputs from an external device and for producing outputs thereto, wherein such inputs and outputs have a second timing characteristic that is different from said first timing characteristic; at least one controller component (14) including transfer means (22) for effecting control instructions and bi-directional parallel data communications between said computational circuit component (16) and such external device.
Claim 2
Dependent Claim
92 words
A computational system (10) for use with a host processor (12) having a memory unit (12a) therein, comprising: at least one single-instruction multiple-data (SIMD) computational circuit component (16) having a first timing characteristic for processing inputs from an external device and for producing outputs thereto, wherein such inputs and outputs have a second timing characteristic that is different from said first timing characteristic; at least one controller component (14) including transfer means (22) for effecting control instructions and bi-directional parallel data communications between said computational circuit component (16) and such external device.
Claim 3
Dependent Claim
35 words
The computational system of claim 1 which includes first multiplexing means (28) for selectively routing a data stream which is generated outside of the computational system (10) directly to said SIMD computational circuit component (16).
Claim 4
Dependent Claim
28 words
The computational system of claim 2 which includes second multiplexing means (26) for directly routing a data stream to/from said controller component (14) from a data generating/using device.
Claim 5
Dependent Claim
28 words
The computational system of claim 3 which includes direct input means (300) for directly routing a data stream from a data-generating device (304) to said controller component (14).
Claim 6
Dependent Claim
30 words
The computational system of claim 4 which includes a direct output means (302) for directly routing a data stream from said controller component (14) to a data-using device (330, 332).
Claim 7
Dependent Claim
16 words
The computational system of claim 3 wherein said data generating/using device is another controller component (72).
Claim 8
Dependent Claim
35 words
The computational system of claim 2 wherein said first multiplexing means includes means (74d, 76d, . . . ) for routing a data stream from said computational circuit component (16) directly to a data-using device.
Claim 9
Dependent Claim
58 words
The computational system of claim 1 wherein said controller component (14) includes and arithmetic logic unit (54) and wherein address locations for instructions and data which are acted upon by said SIMD computational circuit component (16) are generated by said arithmetic logic unit (54), which is operable to generate address locations in the host processor memory unit (12a).
Claim 10
Dependent Claim
31 words
The computational system of claim 8 wherein said arithmetic logic unit (54) includes means for sequentially addressing portions of data in a data stream in the host processor memory unit (12a).
Claim 11
Dependent Claim
66 words
The computational system of claim 9 which includes I/O buffers (44, 50) and wherein said means for sequentially addressing includes pointer means for setting pointers in said I/O buffers (44, 50), including addresses generated by said arithmetic logic unit (54), said pointer means being operable to define a window (210) delimiting a portion of data in a data stream in the host processor memory unit (12a).
Claim 12
Dependent Claim
56 words
The computational system of claim 1 wherein said SIMD computational circuit component (16) includes plural processor nodes (74, 76, . . . 84) for acting upon a data stream and wherein said controller component (14) includes a processor node instruction cache (58) which contains program instructions for said processor nodes (74, 76, . . . 84).
Claim 13
Dependent Claim
36 words
The computational system of claim 11 wherein said controller component (14) includes an instruction sequencer (22) for generating cache addresses and which includes means (92) for looping instructions repeatedly through said SIMD computational circuit component (16).
Claim 14
Dependent Claim
53 words
The computational system of claim 1 wherein said controller component includes a controller memory segment (128) therein and means (59) for selectively operating said controller memory segment (128) as a RAM storage unit or as a memory cache for said pointer means for addressing memory locations in the host processor memory unit (12a).
Claim 15
Dependent Claim
84 words
(Amended) The computational system of claim 1 wherein said controller component (14) includes an output channel (42, 50), for receiving output data from said SIMD computational circuit component (16), and an input channel (40, 44), for sending input data to said computational circuit component (16), which are connected to said SIMD computational circuit component (16), and which further includes a data shunt path (48) in said controller component (14) for routing data from the output channel (42, 50) to the input channel (40, 44).
Claim 16
Dependent Claim
37 words
The computational system of claim 1 which includes bus structure means (18, 34, 40, 42) which direct all signals flowing between the host processor (12) and said SIMD computational circuit component (16) through said controller component (14).
Claim 17
Dependent Claim
27 words
The computational system of claim 1 which includes means for forming a virtual data channel between said SIMD computational circuit component (16) and the host processor (12).
Claim 18
Dependent Claim
23 words
The computational system of claim 1 wherein all state information contained in the controller component (14) is accessible by the host processor (12).
Claim 19
Dependent Claim
141 words
A computational system (10) for use with a host processor (12) having a memory unit (12a) therein, the host processor (12) and the memory unit (12a)providing a memory interface defined by a first timing protocol comprising: at least one single-instruction multiple-data (SIMD) computational circuit component (16) for processing inputs from outside thereof, said computational circuit component (16) defined by a second timing protocol that is different from the first timing protocol of the memory interface; at least one controller component (14) operatively connected with said computational circuit component (16) and with the memory interface, said controller component (14) including transfer means (22) for effecting control instructions and bi-directional parallel data communications between the memory interface and said SIMD computational circuit component (16) and for, synchronizing the events occurring in said computational circuit component (16) with events occurring in the memory interface.
Claim 20
Dependent Claim
141 words
A computational system (10) for use with a host processor (12) having a memory unit (12a) therein, the host processor (12) and the memory unit (12a)providing a memory interface defined by a first timing protocol comprising: at least one single-instruction multiple-data (SIMD) computational circuit component (16) for processing inputs from outside thereof, said computational circuit component (16) defined by a second timing protocol that is different from the first timing protocol of the memory interface; at least one controller component (14) operatively connected with said computational circuit component (16) and with the memory interface, said controller component (14) including transfer means (22) for effecting control instructions and bi-directional parallel data communications between the memory interface and said SIMD computational circuit component (16) and for, synchronizing the events occurring in said computational circuit component (16) with events occurring in the memory interface.
Claim 21
Dependent Claim
35 words
The computational system of claim 18 which includes first multiplexing means (28) for selectively routing a data stream which is generated outside of the computational system (10) directly to said SIMD computational circuit component (16).
Claim 22
Dependent Claim
28 words
The computational system of claim 19 which includes second multiplexing means (26) for directly routing a data stream to/from said controller component (14) from a data generating/using device.
Claim 23
Dependent Claim
28 words
The computational system of claim 20 which includes direct input means (300) for directly routing a data stream from a data-generating device (304) to said controller component (14).
Claim 24
Dependent Claim
30 words
The computational system of claim 21 which includes a direct output means (302) for directly routing a data stream from said controller component (14) to a data-using device (330, 332).
Claim 25
Dependent Claim
16 words
The computational system of claim 20 wherein said data generating/using device is another controller component (72).
Claim 26
Dependent Claim
36 words
The computational system of claim 19 wherein said first multiplexing means includes means (74d, 76d, . . . ) for routing a data stream from said SIMD computational circuit component (16) directly to a data-using device.
Claim 27
Dependent Claim
26 words
The computational system of claim 18 wherein all signals flowing between the host processor (12) and said computational circuit component (16) transit said controller component (14).
Claim 28
Dependent Claim
26 words
The computational system of claims 25, 19 or 20 which includes means for synchronizing data prior to routing data to a SIMD computational circuit component (16).
Claim 29
Dependent Claim
56 words
The computational system of claim 18 wherein said controller component (14) includes and arithmetic logic unit (54) and wherein address locations for instructions and data which are acted upon by said computational component (16) are generated by said arithmetic logic unit (54), which is operable to generate address locations in the host processor memory unit (12a).
Claim 30
Dependent Claim
31 words
The computational system of claim 27 wherein said arithmetic logic unit (54) includes means for sequentially addressing portions of data in a data stream in the host processor memory unit (12a).
Claim 31
Dependent Claim
62 words
The computational system of claim 28 which includes I/O buffers (44, 50) and wherein said means for sequentially addressing includes pointer means for setting pointers in said I/O buffers (44, 50), including addresses generated by said arithmetic logic unit (54), and for defining a window (210) delimiting a portion of data in a data stream in the host processor memory unit (12a).
Claim 32
Dependent Claim
56 words
The computational system of claim 18 wherein said SIMD computational circuit component (16) includes plural processor nodes (74, 76, . . . 84) for acting upon a data stream and wherein said controller component (14) includes a processor node instruction cache (58) which contains program instructions for said processor nodes (74, 76, . . . 84).
Claim 33
Dependent Claim
36 words
The computational system of claim 30 wherein said controller component (14) includes an instruction sequencer (22) for generating cache addresses and which includes means (92) for looping instructions repeatedly through said SIMD computational circuit component (16).
Claim 34
Dependent Claim
81 words
The computational system of claim 18 wherein said controller component (14) includes an output channel (42, 50), for receiving output data from said computational circuit component (16), and an input channel (40, 44), for sending input data to said computational circuit component (16), which are connected to said computational circuit component (16), and which further includes a data shunt path (48) in said controller component (14) for routing data from said output channel (42, 50) to said input channel (40, 44).
Claim 35
Dependent Claim
53 words
The computational system of claim 18 wherein said controller component includes a controller memory segment (128) therein and means (59) for selectively operating said controller memory segment (128) as a RAM storage unit or as a memory cache for said pointer means for addressing memory locations in the host processor memory unit (12a).
Claim 36
Dependent Claim
27 words
The computational system of claim 18 which includes means for forming a virtual data channel between said SIMD computational circuit component (16) and the host processor (12).
Claim 37
Dependent Claim
23 words
The computational system of claim 18 wherein all state information contained in said controller component (14) is accessible by the host processor (12).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-01-22 | 1999-07-24 | 2000-01-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-01-22 | 2003-07-24 | 2004-01-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-01-22 | 2007-07-24 | 2008-01-23 | $7700.00 | Window Closed / Lapsed |