Data processor calculating branch target address of a branch instruction in parallel with decoding of the instruction

Claim 2

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field and branches to an address obtained by adding a value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit and outputting a decoded result; an instruction execution unit for executing the instructions on the basis of the said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the instruction being decoded in said instruction decoding unit; and a branch target address calculation unit including first adding means for calculating a first address in parallel with decoding of a first instruction in said instruction decoding unit, by adding a value of the first branch displacement field of said first instruction inputted from said instruction fetch unit, and an address of said first instruction inputted from said program counter, said first adding means starting calculation of said first address before said first instruction is identified as said first branch instruction, second adding means for calculating a second address in parallel with decoding of said first instruction in said instruction decoding unit, by adding a value of the second branch displacement field of said first instruction inputted from said instruction fetch unit, and an address of said first instruction inputted from said program counter, said second adding means starting calculation of said second address before said first instruction is identified as said second branch instruction, and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.

Claim 3

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field and branches to an address obtained by adding a value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, outputting a decoded result, and outputting a value of said second branch displacement field when the decoded instruction is said second branch instruction; an instruction execution unit for executing the instructions on the basis of said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the instruction being decoded in said instruction decoding unit; and a branch target address calculation unit including adding means (a) for calculating a first address in parallel with decoding of a first instruction in said instruction decoding unit, by adding a value of said first branch displacement field of said first instruction inputted from said instruction fetch unit, and an address of said first instruction inputted from said program counter, said adding means starting calculation of said first address before said first instruction is identified as said first branch instruction, and (b) for calculating a second address after calculating said first address, by adding a value of said second branch displacement field of said first instruction inputted from said instruction decoding unit, and an address of said first instruction inputted from said program counter, when said first instruction is said second branch instruction; and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.

Claim 4

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field and branches to an address obtained by adding a value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, outputting a decoded result, and outputting a value of said second branch displacement field when the decoded instruction is said second branch instruction; an instruction execution unit for executing the instructions on the basis of said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the instruction being decoded in said instruction decoding unit; and a branch target address calculation unit including adding means (a) for calculating a first address in parallel with decoding of a first instruction in said instruction decoding unit, by adding a value of said first branch displacement field of said first instruction inputted from said instruction fetch unit, and an address of said first instruction inputted from said program counter, said adding means starting calculation of said first address before said first instruction is identified as said first branch instruction, and (b) for calculating a second address after calculating said first address, by adding a value of said second branch displacement field of said first instruction inputted from said instruction decoding unit, and an address of said first instruction inputted from said program counter, when said first instruction is said second branch instruction; and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.

Claim 5

A data processor for processing a branch instruction which includes an operation code field and a branch displacement field, and branches to an address obtained by adding a value of said branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit and outputting a decoded result including a code length of the decoded instruction; an instruction execution unit for executing the instructions on the basis of said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the instruction being decoded in said instruction decoding unit; and a branch target address calculation unit including adding means for calculating a first address in parallel with decoding of a first instruction in said instruction decoding unit, by adding a value of said branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a second instruction preceding to said first instruction inputted from said program counter, and said code length of said second instruction inputted from said instruction decoding unit, said adding means stating calculation of said first address before said first instruction is identified as said branch instruction; and transferring means for transferring said first address to said instruction fetch unit when said first instruction is said branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said branch instruction.

Claim 6

A data processor for processing a branch instruction which includes an operation code field and a branch displacement field, and branches to an address obtained by adding a value of said branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit and outputting a decoded result including a code length of the decoded instruction; an instruction execution unit for executing the instructions on the basis of said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the instruction being decoded in said instruction decoding unit; and a branch target address calculation unit including adding means for calculating a first address in parallel with decoding of a first instruction in said instruction decoding unit, by adding a value of said branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a second instruction preceding to said first instruction inputted from said program counter, and said code length of said second instruction inputted from said instruction decoding unit, said adding means stating calculation of said first address before said first instruction is identified as said branch instruction; and transferring means for transferring said first address to said instruction fetch unit when said first instruction is said branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said branch instruction.

Claim 7

A data processor for processing a branch instruction which includes an operation code field and a branch displacement field, and branches to an address obtained by adding a value of said branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, dividing one instruction into one or a plural number of unit processing codes, processing one of said unit processing code in one decoding processing, and for outputting a decoded result including a code length of the decoded unit processing code; an instruction execution unit for executing the instructions on the basis of the said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the unit processing code decoded in said instruction decoding unit; and a branch target address calculation unit including adding means, including a three input adder, for calculating a first address in parallel with decoding of a first unit processing code of a first instruction in said instruction decoding unit, by adding a value of said branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a last unit processing code of a second instruction preceding to said first instruction inputted from said program counter, and said code length of said last unit processing code inputted from said instruction decoding unit, said adding means stating calculation of said first address before said first instruction is identified as said branch instruction; and transferring means for transferring said first address to said instruction fetch unit when said first instruction is said branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said branch instruction.

Claim 8

A data processor for processing a branch instruction which includes an operation code field and a branch displacement field, and branches to an address obtained by adding a value of said branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, dividing one instruction into one or a plural number of unit processing codes, processing one of said unit processing code in one decoding processing, and for outputting a decoded result including a code length of the decoded unit processing code; an instruction execution unit for executing the instructions on the basis of the said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the unit processing code decoded in said instruction decoding unit; and a branch target address calculation unit including adding means, including a three input adder, for calculating a first address in parallel with decoding of a first unit processing code of a first instruction in said instruction decoding unit, by adding a value of said branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a last unit processing code of a second instruction preceding to said first instruction inputted from said program counter, and said code length of said last unit processing code inputted from said instruction decoding unit, said adding means stating calculation of said first address before said first instruction is identified as said branch instruction; and transferring means for transferring said first address to said instruction fetch unit when said first instruction is said branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said branch instruction.

Claim 9

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field, and branches to an address obtained by adding a value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, dividing one instruction into one or a plural number of unit processing codes, processing one of said unit processing code in one decoding processing, and outputting a decoded result including a code length of the decoded unit processing code; an instruction execution unit for executing the instructions on the basis of said decoded results inputted from said instruction decoding unit; a program counter for holding an address of the unit processing code decoded in said instruction decoding unit; and a branch target address calculation unit including first adding means, including a first three input adder, for calculating a first address in parallel with decoding of a first unit processing code of a first instruction in said instruction decoding unit, by adding a value of said first branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a last unit processing code of a second instruction preceding to said first instruction inputted from said program counter, and a code length of said last unit processing code inputted from said instruction decoding unit, said first adding means stating calculation of said first address before said first instruction is identified as said first branch instruction; second adding means, including a second three input adder, for calculating a second address in parallel with decoding of said first unit processing code of said first instruction in said instruction decoding unit, by adding a value of said second branch displacement field of said first instruction inputted from said instruction fetch unit, the address of said last unit processing code of said second instruction inputted from said program counter, and said code length of said last unit processing code inputted from said instruction decoding unit, said second adding means stating calculation of said second address before said first instruction is identified as said second branch instruction; and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.

Claim 10

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field, and branches to an address obtained by adding a value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, dividing one instruction into one or a plural number of unit processing codes, processing one of said unit processing code in one decoding processing, and outputting a decoded result including a code length of the decoded unit processing code; an instruction execution unit for executing the instructions on the basis of said decoded results inputted from said instruction decoding unit; a program counter for holding an address of the unit processing code decoded in said instruction decoding unit; and a branch target address calculation unit including first adding means, including a first three input adder, for calculating a first address in parallel with decoding of a first unit processing code of a first instruction in said instruction decoding unit, by adding a value of said first branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a last unit processing code of a second instruction preceding to said first instruction inputted from said program counter, and a code length of said last unit processing code inputted from said instruction decoding unit, said first adding means stating calculation of said first address before said first instruction is identified as said first branch instruction; second adding means, including a second three input adder, for calculating a second address in parallel with decoding of said first unit processing code of said first instruction in said instruction decoding unit, by adding a value of said second branch displacement field of said first instruction inputted from said instruction fetch unit, the address of said last unit processing code of said second instruction inputted from said program counter, and said code length of said last unit processing code inputted from said instruction decoding unit, said second adding means stating calculation of said second address before said first instruction is identified as said second branch instruction; and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.

Claim 11

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field, and branches to an address obtained by adding value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, dividing one instruction into one or a plural number of unit processing codes, processing one of said unit processing code in one decoding processing, outputting a decoded result including a code length of the decoded unit processing code, and outputting a value of said second branch displacement field when the decoded instruction is said second branch instruction; an instruction execution unit for executing the instructions on the basis of said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the unit processing code decoded in said instruction decoding unit; and a branch target address calculation unit including adding means, including a three input adder, (a) for calculating a first address in parallel with decoding of a first unit processing code of a first instruction in said instruction decoding unit, by adding a value of said first branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a last unit processing code of a second instruction preceding to said first instruction inputted from said program counter, and said code length of said last unit processing code inputted from said instruction decoding unit, said adding means starting calculation of said first address before said first instruction is identified as said first branch instruction and (b) for calculating a second address after calculating said first address, by adding a value of said second branch displacement field of said first instruction inputted from said instruction decoding unit, and an address of said first instruction inputted from said program counter, when said first instruction is said second branch instruction; and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.

Claim 12

A data processor for processing a first branch instruction which includes a first operation code field and a first branch displacement field, and branches to an address obtained by adding value of said first branch displacement field to its address, and a second branch instruction which includes a second operation code field and a second branch displacement field different from said first displacement field, and branches to an address obtained by adding a value of said second branch displacement field to its address, comprising: a memory for storing instructions; an instruction fetch unit for fetching the instructions from said memory; an instruction decoding unit for decoding the instructions fetched by said instruction fetch unit, dividing one instruction into one or a plural number of unit processing codes, processing one of said unit processing code in one decoding processing, outputting a decoded result including a code length of the decoded unit processing code, and outputting a value of said second branch displacement field when the decoded instruction is said second branch instruction; an instruction execution unit for executing the instructions on the basis of said decoded result inputted from said instruction decoding unit; a program counter for holding an address of the unit processing code decoded in said instruction decoding unit; and a branch target address calculation unit including adding means, including a three input adder, (a) for calculating a first address in parallel with decoding of a first unit processing code of a first instruction in said instruction decoding unit, by adding a value of said first branch displacement field of said first instruction inputted from said instruction fetch unit, an address of a last unit processing code of a second instruction preceding to said first instruction inputted from said program counter, and said code length of said last unit processing code inputted from said instruction decoding unit, said adding means starting calculation of said first address before said first instruction is identified as said first branch instruction and (b) for calculating a second address after calculating said first address, by adding a value of said second branch displacement field of said first instruction inputted from said instruction decoding unit, and an address of said first instruction inputted from said program counter, when said first instruction is said second branch instruction; and transferring means for selectively transferring said first and second address to said instruction fetch unit in accordance with a part of said decoded result of said first instruction, said transferring means transferring said first address when said first instruction is said first branch instruction, and transferring said second address when said first instruction is said second branch instruction, wherein said instruction fetch unit fetches an instruction of said first address when said first instruction is said first branch instruction, and fetches an instruction of said second address when said first instruction is said second branch instruction.