US5295248A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Branch control circuit
Assignee: Toshiba Corp
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Filing: 1990-10-15
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Granted: 1994-03-15
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Expires: 2010-10-15
Abstract
Abstract A branch prediction control circuit has a register. A main memory provides a machine language instruction to the register and an instruction buffer. The prediction control circuit decodes the instruction held in the register and predicts whether or not the branch is taken. If the instruction is a relative branch instruction, a sum of the address of the instruction and a displacement included in the instruction is computed to provide a branch address. At the same time, a branch address valid signal is provided. With this arrangement, reliable branch prediction of the relative branch instruction is realized with a small amount of hardware.
Inventors
- 👤 Takashi Miyamori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:27
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/32; G06F9/322; G06F9/324; G06F9/3802; G06F9/3804; G06F9/3836; G06F9/3842; G06F9/3844
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
235 words
A branch prediction control circuit comprising: an instruction fetch circuit for holding a fetch address and fetching an instruction together with branch information about branch prediction; a sub-decoding circuit connected to said instruction fetch circuit for receiving the fetch address and the instruction corresponding to the fetch address together with the branch information, said sub-decoding circuit comprising a first adder for generating a branch address by adding a displacement included in the instruction to said fetch address and a branch instruction decoder for outputting a first branch address valid signal indicative that said branch address is valid if the instruction is a short format relative branch instruction and predicted to be taken; an instruction buffer for holding the fetch address and fetching the instruction together with the branch information at the same time as said sub-decoding circuit; and a main decoding circuit comprising a decoder for receiving the instruction together with the branch information and decoding the instruction in order to enable execution of the instruction, a first selector for selecting a field corresponding to the displacement of the instruction, a second adder for generating a branch address by adding the displacement outputted from said selector to the address of the instruction, said main decoding circuit outputting a second branch address valid signal indicative that the branch address is valid if the instruction is a general format relative branch instruction and predicted to be taken.
Claim 2
Dependent Claim
235 words
A branch prediction control circuit comprising: an instruction fetch circuit for holding a fetch address and fetching an instruction together with branch information about branch prediction; a sub-decoding circuit connected to said instruction fetch circuit for receiving the fetch address and the instruction corresponding to the fetch address together with the branch information, said sub-decoding circuit comprising a first adder for generating a branch address by adding a displacement included in the instruction to said fetch address and a branch instruction decoder for outputting a first branch address valid signal indicative that said branch address is valid if the instruction is a short format relative branch instruction and predicted to be taken; an instruction buffer for holding the fetch address and fetching the instruction together with the branch information at the same time as said sub-decoding circuit; and a main decoding circuit comprising a decoder for receiving the instruction together with the branch information and decoding the instruction in order to enable execution of the instruction, a first selector for selecting a field corresponding to the displacement of the instruction, a second adder for generating a branch address by adding the displacement outputted from said selector to the address of the instruction, said main decoding circuit outputting a second branch address valid signal indicative that the branch address is valid if the instruction is a general format relative branch instruction and predicted to be taken.
Claim 3
Dependent Claim
53 words
The circuit as claimed in claim 1, wherein said subdecoding circuit receives a plurality of instructions together with the branch information and is provided with a second selector for selecting an earliest branch instruction out of the instructions whose branch is predicted to be taken, and outputs said selected instruction to said decoder.
Claim 4
Dependent Claim
230 words
A branch prediction control circuit comprising: a first register for holding at least one machine language instruction fetched from a main memory; a second register for holding an address of the machine language instruction; a first detection circuit connected to said first register, for detecting that the first register contains a relative branch instruction that is predicted to be taken, and provide a branch address valid signal; an adder for adding a displacement included in the relative branch instruction to the address held in said second register, and providing a branch address; an instruction buffer for holding a machine language instruction provided by the main memory at the time when the same instruction is provided to said first register; and a main decoding circuit for decoding machine language instructions held in the instruction buffer, the main decoding circuit comprising a third register for holding the machine language instruction provided by the instruction buffer; a fourth register for holding an address of the machine language instruction; a second detection circuit connected to the third register, for decoding the machine language instruction held in the third register to detect whether the machine language instruction is a relative branch instruction, and providing a branch address valid signal; and an adder for adding a displacement included in the relative branch instruction to the address held in the fourth register, and providing a branch address.
Claim 5
Dependent Claim
230 words
A branch prediction control circuit comprising: a first register for holding at least one machine language instruction fetched from a main memory; a second register for holding an address of the machine language instruction; a first detection circuit connected to said first register, for detecting that the first register contains a relative branch instruction that is predicted to be taken, and provide a branch address valid signal; an adder for adding a displacement included in the relative branch instruction to the address held in said second register, and providing a branch address; an instruction buffer for holding a machine language instruction provided by the main memory at the time when the same instruction is provided to said first register; and a main decoding circuit for decoding machine language instructions held in the instruction buffer, the main decoding circuit comprising a third register for holding the machine language instruction provided by the instruction buffer; a fourth register for holding an address of the machine language instruction; a second detection circuit connected to the third register, for decoding the machine language instruction held in the third register to detect whether the machine language instruction is a relative branch instruction, and providing a branch address valid signal; and an adder for adding a displacement included in the relative branch instruction to the address held in the fourth register, and providing a branch address.
Claim 6
Dependent Claim
66 words
A branch prediction control circuit as claimed in claim 3, wherein the second detection circuit refers to a branch information bit which is added to the machine language instruction to indicate whether or not the branch is taken, provides a signal indicating that the branch address provided by the adder is valid, and decodes an operation code of the machine language instruction into an internal instruction.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-14 | 1997-09-13 | 1998-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-14 | 2001-09-13 | 2002-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-14 | 2005-09-13 | 2006-03-15 | $7700.00 | Window Closed / Lapsed |