System for reexecuting branch instruction without fetching by storing target instruction control information

Claim 2

A data processing apparatus comprising: a main storage in which instructions to be executed are stored; means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information, obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information and said content of the target instruction in response to the address of said branch instruction, and for sending said read out control information and said read out content of the target instruction to said means for executing without an additional fetch of the target instruction from said main storage when re-executing the branch instruction.

Claim 3

A data processing apparatus in accordance with claim 1 wherein said first memory is an associative memory, the control information and the content of the target instruction are written in data fields of the associative memory, the address of the branch instruction is written in an index field of the associative memory and wherein the control information, the content of the target instruction and the address of the branch instruction are written into the associative memory by a single entry number.

Claim 4

A data processing apparatus in accordance with claim 1, wherein said decoding and generating means includes means for sending a signal for requesting an instruction to be decoded to said means for fetching when said first memory has been accessed with the address of a branch instruction and no address of the branch instruction exists in the first memory, and said means for sending a signal does not send a signal when said first memory has been accessed with the address of the branch instruction and the address of the branch instruction exists therein.

Claim 5

A data processing apparatus in accordance with claim 1, wherein said means for executing executes said target instruction according to the control information stored in said first memory.

Claim 6

A data processing apparatus in accordance with claim 1, wherein said means for fetching further includes: a second memory for storing a plurality of instructions and a plurality of addresses corresponding to said plurality of instructions.

Claim 7

A data processing apparatus comprising: a main storage in which instructions to be executed are stored; means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing content of a target instruction accessed by a target address obtained from a branch instruction, for storing an address of an instruction immediately following the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said content of said target instruction, said address of said instruction immediately following said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said content of the target instruction and said address of said instruction immediately following said target instruction in response to the address of said branch instruction, for sending said read out content of the target instruction to said means for executing, and for sending said read out address of said instruction immediately following said target instruction to said means for fetching without an additional fetch of the target instruction from said main storage.

Claim 8

A data processing apparatus comprising: a main storage in which instructions to be executed are stored; means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing content of a target instruction accessed by a target address obtained from a branch instruction, for storing an address of an instruction immediately following the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said content of said target instruction, said address of said instruction immediately following said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said content of the target instruction and said address of said instruction immediately following said target instruction in response to the address of said branch instruction, for sending said read out content of the target instruction to said means for executing, and for sending said read out address of said instruction immediately following said target instruction to said means for fetching without an additional fetch of the target instruction from said main storage.

Claim 9

A data processing apparatus in accordance with claim 6, wherein said first memory is an associative memory, the content of the target instruction and the address of an instruction immediately following the address of the target instruction are written in data fields of the associative memory, the address of the branch instruction is written in an index field of the associative memory, and wherein the content of the target instruction, the address of the instruction immediately following the address of the target instruction are written into the associative memory by a single entry number.

Claim 10

A data processing apparatus in accordance with claim 6 wherein said decoding and generating means includes means for sending a signal for requesting an instruction to be decoded to said means for fetching when said first memory has been accessed with the address of a branch instruction and no address of the branch instruction exists in the first memory and said means for sending a signal does not send a signal when said first memory has been accessed with the address of the branch instruction and the address of the branch instruction exists therein.

Claim 11

A data processing apparatus in accordance with claim 6, wherein said first memory further stores control information, obtained by decoding said target instruction, and wherein said means for executing executes said target instruction according to the control information stored in the memory.

Claim 12

A data processing apparatus in accordance with claim 6, wherein said means for fetching further includes: a second memory for storing a plurality of instructions and a plurality of addresses corresponding to said plurality of instructions.

Claim 13

A data processing apparatus comprising: a main storage in which instructions to be executed are stored; means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, for storing the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction, said address of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information, said content of the target instruction and said address of said target instruction in response to the address of said branch instruction, and for sending said read out address of said target instruction to comparator means, said comparator means compares said read out address of said target instruction with an address of said target instruction generated from said means for executing, when a coincidence is detected by said comparator means said read out control information and said read out content of the target instruction are sent to said means for executing in response to an output of said comparator means without an additional fetch of the target instruction from the main storage when re-executing the branch instruction.

Claim 14

A data processing apparatus comprising: a main storage in which instructions to be executed are stored; means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, for storing the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction, said address of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information, said content of the target instruction and said address of said target instruction in response to the address of said branch instruction, and for sending said read out address of said target instruction to comparator means, said comparator means compares said read out address of said target instruction with an address of said target instruction generated from said means for executing, when a coincidence is detected by said comparator means said read out control information and said read out content of the target instruction are sent to said means for executing in response to an output of said comparator means without an additional fetch of the target instruction from the main storage when re-executing the branch instruction.

Claim 15

A data processing apparatus in accordance with claim 11, wherein said first memory is an associative memory, the control information, the content of the target instruction and the address of the target instruction are written in data fields of the associative memory, the address of the branch instruction is written in an index field of the associative memory, and wherein the control information, the content of the target instruction, the address of the target instruction and the address of the branch instruction are written into the associative memory by a single entry number.

Claim 16

A data processing apparatus in accordance with claim 11, wherein said decoding and generating means includes means for sending a signal for requesting an instruction to be decoded to said means for fetching when said first memory has been accessed with the address of a branch instruction and no address of the branch instruction exists in the first memory, and said means for sending a signal does not send a signal when said first memory has been accessed with the address of the branch instruction and the address of the branch instruction exists therein.

Claim 17

A data processing apparatus in accordance with claim 11, wherein said means for executing executes said target instruction according to the control information stored in said first memory.

Claim 18

A data processing apparatus in accordance with claim 11, wherein the address of the target instruction read out from said first memory is compared with an address of a next instruction calculated by said means for executing.

Claim 19

A data processing apparatus in accordance with claim 11, wherein said means for fetching further includes: a second memory for storing a plurality of instructions and a plurality of addresses corresponding to said plurality of instructions.

Claim 20

A microprocessor for use with a main storage in a data processing system with instructions to be executed by the microprocessor being stored in the main storage, the microprocessor comprising: means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information, obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information and said content of the target instruction in response to the address of said branch instruction and for sending said read out control information and said read out content of the target instruction to said means for executing without an additional fetch of the target instruction from said main storage when re-executing the branch instruction.

Claim 21

A microprocessor for use with a main storage in a data processing system with instructions to be executed by the microprocessor being stored in the main storage, the microprocessor comprising: means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information, obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information and said content of the target instruction in response to the address of said branch instruction and for sending said read out control information and said read out content of the target instruction to said means for executing without an additional fetch of the target instruction from said main storage when re-executing the branch instruction.

Claim 22

A microprocessor in accordance with claim 17, wherein said first memory is an associative memory, the control information and the content of the target instruction are written in data fields of the associative memory, the address of the branch instruction is written in an index field of the associative memory, and wherein the control information, the content of the target instruction and the address of the branch instruction are written into the associative memory by a single entry number.

Claim 23

A microprocessor in accordance with claim 17, wherein said decoding and generating means includes means for sending a signal for requesting an instruction to be decoded to said means for fetching when said first memory has been accessed with the address of a branch instruction and no address of the branch instruction exists in the first memory and said means for sending a signal does not send a signal when said first memory has been accessed with the address of the branch instruction and the address of the branch instruction exists therein.

Claim 24

A microprocessor in accordance with claim 1, wherein said means for executing executes said target instruction according to the control information stored in said first memory.

Claim 25

A microprocessor in accordance with claim 17, wherein said means for fetching further includes: a second memory for storing a plurality of instructions and a plurality of addresses corresponding to said plurality of instructions.

Claim 26

A microprocessor for use with a main storage in a data processing system with instructions to be executed by the microprocessor being stored in said main storage, said microprocessor comprising: means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing content of a target instruction accessed by a target address obtained from a branch instruction, for storing an address of an instruction immediately following the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said content of said target instruction, said address of said instruction immediately following said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said content of the target instruction and said address of said instruction immediately following said target instruction in response to the address of said branch instruction, for sending said read out content of the target instruction to said means for executing, and for sending said read out address of said instruction immediately following said target instruction to said means for fetching without an additional fetch of the target instruction from said main storage when re-executing the branch instruction.

Claim 27

A microprocessor for use with a main storage in a data processing system with instructions to be executed by the microprocessor being stored in said main storage, said microprocessor comprising: means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and said means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing content of a target instruction accessed by a target address obtained from a branch instruction, for storing an address of an instruction immediately following the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said content of said target instruction, said address of said instruction immediately following said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said content of the target instruction and said address of said instruction immediately following said target instruction in response to the address of said branch instruction, for sending said read out content of the target instruction to said means for executing, and for sending said read out address of said instruction immediately following said target instruction to said means for fetching without an additional fetch of the target instruction from said main storage when re-executing the branch instruction.

Claim 28

A microprocessor in accordance with claim 22, wherein said first memory is an associative memory, the content of the target instruction and the address of an instruction immediately following the address of the target instruction are written in data fields of the associative memory, the address of the branch instruction is written in an index field of the associative memory, and wherein, the content of the target instruction, the address of the instruction immediately following the address of the target instruction and the address of the branch instruction are written into the associative memory by a single entry number.

Claim 29

A microprocessor in accordance with claim 22, wherein said decoding and generating means includes means for sending a signal for requesting an instruction to be decoded to said means for fetching when said first memory has been accessed with the address of a branch instruction and no address of the branch instruction exists in the first memory and said means for sending a signal does not send a signal when said first memory has been accessed with the address of the branch instruction and the address of the branch instruction exists therein.

Claim 30

A microprocessor in accordance with claim 27, wherein said first memory further stores control information, obtained by decoding said target instruction and wherein said means for executing executes said target instruction according to the control information stored in the first memory.

Claim 31

A microprocessor in accordance with claim 22, wherein said means for fetching further includes: a second memory for storing a plurality of instructions and a plurality of addresses corresponding to said plurality of instructions.

Claim 32

A microprocessor for use with a main storage in a data processing system with instructions to be executed by the microprocessor being stored in said main storage, said microprocessor comprising: means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and the means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, for storing the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction, said address of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information, said content of the target instruction and said address of said target instruction in response to the address of said branch instruction, and for sending said read out address of said target instruction to comparator means, said comparator means compares said read out address of said target instruction with an address of said target instruction generated from said means for executing, when a coincidence is detected by said comparator means, said read out control information and said read out content of the target instruction are sent to said means for executing in response to an output of said comparator means without an additional fetch of the target instruction from the main storage when re-executing the branch instruction.

Claim 33

A microprocessor for use with a main storage in a data processing system with instructions to be executed by the microprocessor being stored in said main storage, said microprocessor comprising: means, coupled to the main storage, for fetching instructions from said main storage; decoding and generating means, coupled to the means for fetching, for decoding the instructions fetched by the means for fetching and for generating control information for executing the instructions; means, coupled to the decoding and generating means, for executing the instructions in response to the control information generated by the decoding and generating means; said means for fetching, said means for decoding and generating, and the means for executing operating in parallel to perform pipeline data processing; and said decoding and generating means including a first memory for storing said control information obtained from said decoding and generating means by decoding a target instruction accessed by a target address obtained from a branch instruction, for storing content of the target instruction, for storing the address of the target instruction, and for storing an address of said branch instruction, said first memory stores said control information, said content of said target instruction, said address of said target instruction and said address of said branch instruction before re-executing the branch instruction, said first memory further includes means for reading out said control information, said content of the target instruction and said address of said target instruction in response to the address of said branch instruction, and for sending said read out address of said target instruction to comparator means, said comparator means compares said read out address of said target instruction with an address of said target instruction generated from said means for executing, when a coincidence is detected by said comparator means, said read out control information and said read out content of the target instruction are sent to said means for executing in response to an output of said comparator means without an additional fetch of the target instruction from the main storage when re-executing the branch instruction.

Claim 34

A microprocessor in accordance with claim 27, wherein said first memory is an associative memory, the control information and the content of the target instruction are written in data fields of the associative memory, the address of the branch instruction is written in an index field of the associative memory, and wherein the control information, the content of the target instruction, the address of the target instruction and the address of the branch instruction are written into the associative memory by a single entry number.

Claim 35

A microprocessor in accordance with claim 27 wherein said decoding and generating means includes means for sending a signal for requesting an instruction to be decoded to said means for fetching when said first memory has been accessed with the address of a branch instruction and no address of the branch instruction exists in the first memory and said means for sending a signal does not send a signal when said first memory has been accessed with the address of the branch instruction and the address of the branch instruction exists therein.

Claim 36

A microprocessor in accordance with claim 27, wherein said means for executing executes target instruction according to the control information stored in said first memory.

Claim 37

A microprocessor in accordance with claim 28, wherein the address of the target instruction read out from said first memory is compared with an address of a next instruction calculated by said means for executing.

Claim 38

A microprocessor in accordance with claim 27, wherein said means for fetching further includes: a second memory for storing a plurality of instructions and a plurality of addresses corresponding to said plurality of instructions.