Pipeline microcomputer having branch instruction detector and bus controller for producing and carrying branch destination address prior to instruction execution

Claim 2

A microcomputer for use in combination with a memory which memorizes a sequence of instruction codes and a sequence of data signals, said instruction codes comprising ordinary instructions and branch instructions, said microcomputer comprising: (a) bus control means coupled to said memory for accessing said memory to selectively control a write-in operation and a readout operation of said memory and to thereby write and read each of the instruction codes and the data signals into and out of said memory as a write-in instruction code and a readout instruction code, respectively; (b) instruction code memorizing means coupled to said bus control means for successively memorizing said readout instruction code read out of said memory through said bus control means to produce the readout instruction code memorized therein as an execution instruction code; (c) instruction execution means successively supplied from said instruction code memorizing means with said execution instruction code for executing said execution instruction code in a pipeline fashion independently of said write-in and said readout operations carried out in said bus control means; (d) branch instruction detecting means, supplied with said readout instruction code from said bus control means, for detecting whether or not said readout instruction code specifies said branch instruction to produce a branch destination instruction request signal on detection of said branch instruction before said branch instruction is executed in said instruction execution means in said pipeline fashion; (e) address calculation means, supplied with said readout instruction code from said bus control means, for calculating a branch destination address of said memory from said readout instruction code; (f) means for supplying said branch destination address and said branch destination instruction request signal to said bus control means; and (g) said bus control means being for carrying out said readout operation from said branch destination address prior to execution of said branch instruction in said instruction execution means.

Claim 3

A microcomputer as claimed in claim 1, said branch destination address being defined by a sum of a reference address of the readout instruction and a displacement derived from the readout instruction, wherein said address calculation means comprises: means for storing said reference address; and means for calculating said sum of the reference address and said displacement.

Claim 4

A microcomputer for use in combination with a memory which memorizes a sequence of instruction codes and a sequence of data signals, said instruction codes comprising ordinary instructions and branch instructions, said microcomputer comprising: (a) bus control means coupled to said memory for accessing said memory to selectively control a write-in operation and a readout operation of said memory and to thereby write and read each of the instruction codes and the data signals into and out of said memory as a write-in instruction code and a readout instruction code, respectively; (b) instruction code memorizing means, coupled to said bus control means, for successively memorizing said readout instruction code read out of said memory through said bus control means to produce the readout instruction code memorized therein as an execution instruction code; (c) instruction execution means successively supplied from said instruction code memorizing means with said execution instruction code for executing said execution instruction code in a pipeline fashion independently of said write-in and said readout operations carried out in said bus control means; (d) branch instruction detecting means, supplied with said readout instruction code from said bus control means, for detecting whether or not said readout instruction code specifies said branch instruction to produce a branch destination instruction request signal on detection of said branch instruction before the branch instruction is executed in said instruction execution means in said pipeline fashion; (e) a pointer buffer for holding a reference address derived from said readout instruction code to produce a held reference address; (f) a buffer selector for selecting either one of said reference address and said held reference address to produce a first selected address; (g) a fixed value generator for generating a fixed value; (h) an additional selector, responsive to said fixed value and said readout instruction code sent from said bus control means and coupled to said branch instruction detecting means, for selecting either one of said fixed value and a readout address derived from said readout instruction code as a second selected address; (i) an address adder for summing up said first selected address and said second selected address to produce a sum address which specifies a branch destination address of said branch destination instruction code; and (j) means for supplying said sum address to said bus control means; (k) said bus control means being for carrying out said readout operation from said sum address prior to execution of said branch instruction in said instruction execution means.

Claim 5

A microcomputer for use in combination with a memory which memorizes a sequence of instruction codes and a sequence of data signals, said instruction codes comprising ordinary instructions and branch instructions, said microcomputer comprising: (a) bus control means coupled to said memory for accessing said memory to selectively control a write-in operation and a readout operation of said memory and to thereby write and read each of the instruction codes and the data signals into and out of said memory as a write-in instruction code and a readout instruction code, respectively; (b) instruction code memorizing means, coupled to said bus control means, for successively memorizing said readout instruction code read out of said memory through said bus control means to produce the readout instruction code memorized therein as an execution instruction code; (c) instruction execution means successively supplied from said instruction code memorizing means with said execution instruction code for executing said execution instruction code in a pipeline fashion independently of said write-in and said readout operations carried out in said bus control means; (d) branch instruction detecting means, supplied with said readout instruction code from said bus control means, for detecting whether or not said readout instruction code specifies said branch instruction to produce a branch destination instruction request signal on detection of said branch instruction before the branch instruction is executed in said instruction execution means in said pipeline fashion; (e) a pointer buffer for holding a reference address derived from said readout instruction code to produce a held reference address; (f) a buffer selector for selecting either one of said reference address and said held reference address to produce a first selected address; (g) a fixed value generator for generating a fixed value; (h) an additional selector, responsive to said fixed value and said readout instruction code sent from said bus control means and coupled to said branch instruction detecting means, for selecting either one of said fixed value and a readout address derived from said readout instruction code as a second selected address; (i) an address adder for summing up said first selected address and said second selected address to produce a sum address which specifies a branch destination address of said branch destination instruction code; and (j) means for supplying said sum address to said bus control means; (k) said bus control means being for carrying out said readout operation from said sum address prior to execution of said branch instruction in said instruction execution means.