Transfer control unit, processor element and data transferring method

Claim 2

A transfer control unit which receives an address signal and a data signal from a first external unit via an address bus and a data bus, respectively, to transfer them to a second external unit, comprising: a buffer for temporarily storing data; an address register for being written to, from the first external unit via the data bus; an address generating part, connected to the address register, for sequentially generating addresses of a memory in accordance with a written value of the address register; a comparator for comparing an address generated in the address generating part with an address inputted from the first external unit via the address bus to output a coincidence signal when the addresses coincide with each other; and a controller, connected to the comparator, the buffer and the address generating part, for commanding the buffer to store the inputted data from the first external unit via the data bus and commanding the address generating part to proceed to a next address upon receipt of the coincidence signal output by the comparator, wherein said first external unit and said second external unit are external to said transfer control unit.

Claim 3

The transfer control unit according to claim 1, wherein the controller includes: a counter which is connected to the comparator, which counts the number of times the coincidence signal is outputted from the comparator, and which is reset to an initial value when it counts up to a preset value; and a signal generating part, connected to the counter, the buffer, and the address generating part, for generating a signal for commanding the buffer to store the data from the first external unit via the data bus and commanding the address generating part to proceed to a next address when the count of the counter reaches to the preset value.

Claim 4

The transfer control unit according to claim 2, wherein the signal generating part is connected to an output side of the comparator, and the signal generating part commands the buffer to store the data from the first external unit via the data bus and commands the address generating part to proceed to a next address when a count of the counter reaches to the preset value and the coincidence signal from the comparator is received.

Claim 5

A processor element comprising a memory, a processor, and a transfer control unit which are connected to one another via an address bus and a data bus, wherein the transfer control unit includes: a buffer for temporarily storing data; an address register for being written to from an external unit via the data bus; an address generating part, connected to the address register, for sequentially generating addresses in accordance with a written value of the address register; a comparator for comparing an address generated in the address generating part with an address inputted from the external unit via the address bus to output a coincidence signal when the addresses coincide with each other; and a controller, connected to the comparator, the buffer and the address generating part, for commanding the buffer to store data input from the external unit via the data bus and commanding the address generating part to proceed to a next address upon receipt of the coincidence signal output by the comparator, wherein the processor is connected to the comparator of the transfer control unit, and the processor outputs an address signal to the comparator and writes a data into an address in the memory accessed by the address generating part and said memory and said processor are external to said transfer control unit.

Claim 6

A processor element comprising a memory, a processor, and a transfer control unit which are connected to one another via an address bus and a data bus, wherein the transfer control unit includes: a buffer for temporarily storing data; an address register for being written to from an external unit via the data bus; an address generating part, connected to the address register, for sequentially generating addresses in accordance with a written value of the address register; a comparator for comparing an address generated in the address generating part with an address inputted from the external unit via the address bus to output a coincidence signal when the addresses coincide with each other; and a controller, connected to the comparator, the buffer and the address generating part, for commanding the buffer to store data input from the external unit via the data bus and commanding the address generating part to proceed to a next address upon receipt of the coincidence signal output by the comparator, wherein the processor is connected to the comparator of the transfer control unit, and the processor outputs an address signal to the comparator and writes a data into an address in the memory accessed by the address generating part and said memory and said processor are external to said transfer control unit.

Claim 7

The processor element according to claim 4, wherein a part of the memory serves as a transfer region, and the processor sets addresses corresponding to the transfer region to the address register of the transfer control unit, and writes a data into the transfer region at data transfer.

Claim 10

The method of transferring a data according to claim 6, wherein the commanding steps are carried out when a counter reaches to a preset value by counting the number of times the coincidence signal is received.

Claim 11

The transfer control unit according to claim 1, wherein the data bus of the first external unit is different from a data bus of the second external unit.