US5089951A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microcomputer incorporating memory
Assignee: Toshiba Corp
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Filing: 1988-11-02
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Granted: 1992-02-18
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Expires: 2008-11-02
Abstract
Abstract A microcomputer of this invention includes an internal memory. These memories are connected to internal buses and external buses through bi-directional buffers. This microcomputer also includes a buffer controller for determining whether an access by a control section is made to the internal memory or the access is made to an external memory. When the control section accesses the internal memories, the buffer controller controls the directions of the bi-directional buffers to enable data transfer from the external to the internal bus side. When the controller accesses the external memory, bi-directional buffers are controlled to enable data transfer from the internal to the external bus side.
Inventors
- 👤 Yasuo Iijima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 17:42
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/16; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0754; G06F11/076; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
164 words
A microcomputer comprising: memory means for storing data; memory access means for accessing said memory means; input/output means for inputting and outputting data from and to a device external to said microcomputer; output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived form an access operation to said memory means; access source determining means for determining whether access of said memory means is performed by said memory access means or is externally performed through said input/output means; and control means for controlling said output inhibiting means to inhibit external output through said input/output means of said data derived from the access to said memory means when said access source determining determines that the access is performed by said memory access means, and form controlling said output inhibiting means to allow external output through said input/output means of data derived form the access when said access source determining means determines that the access is externally performed.
Claim 2
Dependent Claim
164 words
A microcomputer comprising: memory means for storing data; memory access means for accessing said memory means; input/output means for inputting and outputting data from and to a device external to said microcomputer; output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived form an access operation to said memory means; access source determining means for determining whether access of said memory means is performed by said memory access means or is externally performed through said input/output means; and control means for controlling said output inhibiting means to inhibit external output through said input/output means of said data derived from the access to said memory means when said access source determining determines that the access is performed by said memory access means, and form controlling said output inhibiting means to allow external output through said input/output means of data derived form the access when said access source determining means determines that the access is externally performed.
Claim 3
Dependent Claim
33 words
A microcomputer according to claim 1, wherein said output inhibiting means includes a bi-directional buffer responsive to said control means, and internal bus means for connecting said memory means to said bi-directional buffer.
Claim 4
Dependent Claim
20 words
A microcomputer according to claim 2, wherein said control means includes means for controlling transfer directions of said bi-directional buffer.
Claim 5
Dependent Claim
43 words
A microcomputer according to claim 3, wherein said internal bus means and said input/output means each comprise an access data bus, an address bus, and a data bus, respectively, and said bi-directional buffer is arranged to be coupled with each of said buses.
Claim 6
Dependent Claim
97 words
A microcomputer according to claim 1, wherein said memory means comprises a program memory for storing programs and a data memory for storing data, said control means controlling said output inhibiting means so as to block external output through said input/output means of data read out from said program memory when the access is externally performed to said program memory in a read mode, and so as to allow external output of the data read to from said data memory through said input/output means when the access is performed to said data memory in a read mode.
Claim 7
Dependent Claim
57 words
A microcomputer according to claim 1, wherein said memory means comprises a program memory for storing programs, and a data memory for storing data, and said output inhibiting means inhibits the read data from being externally output through said input/output means when the contents of said program or data memory are read by said memory access means.
Claim 8
Dependent Claim
127 words
A microcomputer comprising: memory means for storing data, the memory means including a program memory for storing a program and a data memory for storing data; memory access means for accessing said memory means; input/output means for inputting and outputting data from and to a device external to said microcomputer; output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived from an access operation to said memory means; control means for controlling said output inhibiting means to block external output through said input/output means of data read out from said memory means when said program memory is accessed, and to allow external output of the data read out from said memory means when said data memory is accessed.
Claim 9
Dependent Claim
127 words
A microcomputer comprising: memory means for storing data, the memory means including a program memory for storing a program and a data memory for storing data; memory access means for accessing said memory means; input/output means for inputting and outputting data from and to a device external to said microcomputer; output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived from an access operation to said memory means; control means for controlling said output inhibiting means to block external output through said input/output means of data read out from said memory means when said program memory is accessed, and to allow external output of the data read out from said memory means when said data memory is accessed.
Claim 10
Dependent Claim
33 words
A microcomputer according to claim 7, wherein said output inhibiting means includes a bi-directional buffer responsive to said control means, and internal bus means for connecting said memory means to said bi-directional buffer.
Claim 11
Dependent Claim
20 words
A microcomputer according to claim 8, wherein said control means includes means for controlling transfer directions of said bi-directional buffer.
Claim 12
Dependent Claim
43 words
A microcomputer according to claim 9, wherein said internal bus means and said input/output means each comprise an access data bus, an address bus, and a data bus, respectively, and said bi-directional buffer is arranged to be coupled with each of said buses.
Claim 13
Independent Claim
140 words
A system for transferring data comprising: a peripheral device capable of receiving and outputting data; and a microcomputer comprising: memory means for storing data, said memory means including a program memory for storing programs and a data memory for storing data, memory access means for accessing said memory means, input/output means for inputting and outputting data from and to said peripheral device, output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived from an access operation to said memory means, and control means for controlling said output inhibiting means to block external output through said input/output means of said data read out from said memory means when said program memory is accessed, and to allow external of the data read out from said memory means when said data memory is accessed.
Claim 14
Independent Claim
140 words
A system for transferring data comprising: a peripheral device capable of receiving and outputting data; and a microcomputer comprising: memory means for storing data, said memory means including a program memory for storing programs and a data memory for storing data, memory access means for accessing said memory means, input/output means for inputting and outputting data from and to said peripheral device, output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived from an access operation to said memory means, and control means for controlling said output inhibiting means to block external output through said input/output means of said data read out from said memory means when said program memory is accessed, and to allow external of the data read out from said memory means when said data memory is accessed.
Claim 15
Dependent Claim
19 words
A system according to claim 11, wherein said peripheral device is a test unit to access said memory means.
Claim 16
Dependent Claim
28 words
A microcomputer according to claim 11, wherein said peripheral device is an external memory, and said memory access means accesses said memory means and said external memory means.
Claim 17
Dependent Claim
63 words
A system according to claim 11, wherein said peripheral device is an external memory, said control means controlling said bi-directional buffer to disable data transfer when said memory access means accesses said memory means, said control means controlling said bi-directional buffer to enable data transfer from said internal bus means to said input/output means when said memory access means read-accesses said external memory.
Claim 18
Dependent Claim
47 words
A microcomputer according to claim 11, wherein said peripheral device is a test unit selectively connected to said microcomputer, said control means controlling said bi-directional buffer to enable data transfer from said input/output means to said internal bus means when said test unit read-accesses said memory means.
Claim 19
Independent Claim
182 words
A system for transferring data comprising: a peripheral device capable of receiving and outputting data; and a microcomputer comprising: memory means for storing data, memory access means for accessing said memory means, input/output means for inputting and outputting data from and to said peripheral device, output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived from an access operation to said memory means, access source determining means for determining whether access of said memory means is performed by said memory access means or is externally performed through said input/output means, and control means for controlling said output inhibiting means to inhibit external output through said input/output means of said data derived from said access to said memory means when said access source determining means determines that the access is performed by said memory access means, and for controlling said output inhibiting means to enable external output through said input/output means of data derived from the access when said access source determining means determines that the access is externally performed by said peripheral device.
Claim 20
Independent Claim
182 words
A system for transferring data comprising: a peripheral device capable of receiving and outputting data; and a microcomputer comprising: memory means for storing data, memory access means for accessing said memory means, input/output means for inputting and outputting data from and to said peripheral device, output inhibiting means, connected to said memory means, for inhibiting external output through said input/output means of data derived from an access operation to said memory means, access source determining means for determining whether access of said memory means is performed by said memory access means or is externally performed through said input/output means, and control means for controlling said output inhibiting means to inhibit external output through said input/output means of said data derived from said access to said memory means when said access source determining means determines that the access is performed by said memory access means, and for controlling said output inhibiting means to enable external output through said input/output means of data derived from the access when said access source determining means determines that the access is externally performed by said peripheral device.
Claim 21
Dependent Claim
33 words
A system according to claim 16, wherein said output inhibiting means includes a bi-directional buffer responsive to said control means, and internal bus means for connecting said memory means to said bi-directional buffer.
Claim 22
Dependent Claim
20 words
A system according to claim 17, wherein said control means includes means for controlling transfer directions of said bi-directional buffer.
Claim 23
Dependent Claim
42 words
A system according to claim 18, wherein said internal bus means and said input/output means each comprise an access data bus, an address bus, and a data bus, respectively, said bi-directional buffer being arranged to be coupled with each of said buses.
Claim 24
Dependent Claim
63 words
A microcomputer according to claim 19, wherein said peripheral device is an external memory, said control means controlling said bi-directional buffer to disable data transfer when said memory access means accesses said memory means, said control means controlling said bi-directional buffer to enable data transfer from said internal bus means to said input/output means when said memory access means read-accesses said external memory.
Claim 25
Dependent Claim
47 words
A microcomputer according to claim 19, wherein said peripheral device is a test unit selectively connected to said microcomputer, said control means controlling said bi-directional buffer to enable data transfer from said input/output means to said internal bus means when said test unit read-accesses said memory means.
Claim 26
Dependent Claim
19 words
A system according to claim 16, wherein said peripheral device is a test unit to access said memory means.
Claim 27
Dependent Claim
26 words
A system according to claim 16, wherein said peripheral device is an external memory and said memory access means accesses said memory and external memory means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |