EP0215464A2
Expired / Lapsed
EP
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Semiconductor integrated circuit device
Assignee: Hitachi Ltd
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Filing: 1986-09-15
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Granted: —
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Expires: 2006-09-15
Abstract
Abstract A semiconductor integrated circuit device inhibits the output of programmed data of its built-in memory (ROM) to an external terminal (TO) but outputs the result of comparison of the programmed data with an input signal supplied from an external terminal (I, I/O) to the external terminal (TO).
Inventors
- 👤 Kiyoshi Matsubara
- 👤 Tadashi Yamaura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 18:56
CPC Classifications
G; G06; G06F; G06F15/00; G06F21/00; G06F21/70; G06F21/78; G06F21/79; G11; G11C; G11C29/00; G11C29/04
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
66 words
A semiconductor integrated circuit device comprising: a memory circuit (ROM) the output of the programmed data of which is inhibited to an external terminal (TO), and a comparing circuit (CMP) for comparing the programmed data read out from said memory circuit (ROM) with an input signal supplied from an external terminal (I, I/O), and outputting the resulting coincidence or discordance signal to said external terminal (TO).
Claim 2
Dependent Claim
66 words
A semiconductor integrated circuit device comprising: a memory circuit (ROM) the output of the programmed data of which is inhibited to an external terminal (TO), and a comparing circuit (CMP) for comparing the programmed data read out from said memory circuit (ROM) with an input signal supplied from an external terminal (I, I/O), and outputting the resulting coincidence or discordance signal to said external terminal (TO).
Claim 3
Dependent Claim
14 words
The device of claim 1, wherein said memory circuit comprises a read-only memory (ROM).
Claim 4
Dependent Claim
40 words
The device of claim 1 or 2, wherein the output of said coincidence or discordance signal is effected once after a plurality of said programmed data are compared with a plurality of said input signals corresponding to said programmed data.
Claim 5
Dependent Claim
20 words
The device of claim 3, wherein said programmed data is read out in the unit of a plurality of bits.
Claim 6
Dependent Claim
30 words
The device of claim 3 or 4, wherein the output of said coincidence or discordance signal is controlled by part of an address signal supplied to said memory circuit (ROM).
Claim 7
Dependent Claim
29 words
The device of claim 3 or 4, wherein the output of said coincidence or discordance signal is controlled by a counter circuit (COUNT) in synchronism with said comparison operation.
Claim 8
Independent Claim
52 words
The device of any of claims 3 to 6, wherein said comparison circuit (CMP) has the functions of comparing said programmed data with said input signal, holding said coincidence or discordance signal, and holding said discordance signal after one discordance signal is generated and inhibiting the reception of subsequent results of comparison.
Claim 9
Independent Claim
50 words
The device of any of claims 1 to 7, which further comprises a microprocessor (CPU) which executes calculation on the basis of said programmed data of said memory circuit (ROM), and wherein said memory circuit (ROM) consists of a read-only memory storing therein programs or data for said microprocessor (CPU).
References Cited (Backward Citations)
No citation records indexed.
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