Semiconductor integrated circuit with internal compensation for changes in time delay

Claim 2

A semiconductor integrated circuit comprising: a clock-synchronized logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; a delay time compensation control circuit connected to said counting means for generating control data based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation; a synchronizing clock timing compensation circuit connected to and receiving the control data from said delay time compensation control circuit for generating an output signal supplied to said logic circuit for compensating for a change in the signal propagation delay of said logic circuit; and an oscillation delay control circuit connected to and receiving the control data from said delay time compensation control circuit for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator.

Claim 3

A semiconductor integrated circuit comprising: a logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring,, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; a delay time compensation control circuit connected to said counting means for generating a compensation voltage based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation; and a power-supply voltage control circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for controlling a power-supply voltage applied to said logic circuit and said ring oscillator to compensate for a change in the propagation delay of said logic circuit.

Claim 4

A semiconductor integrated circuit comprising: a logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring,, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; a delay time compensation control circuit connected to said counting means for generating a compensation voltage based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation; and a power-supply voltage control circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for controlling a power-supply voltage applied to said logic circuit and said ring oscillator to compensate for a change in the propagation delay of said logic circuit.

Claim 5

A combination of semiconductor integrated circuits comprising: a plurality of semiconductor integrated circuits, each of said semiconductor integrated circuits comprising: a clock-synchronized logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements, and a plurality of dummy device elements connected in series, wherein said logic circuits of said plurality of semiconductor integrated circuits are connected in series and said plurality of dummy device elements of said plurality of semiconductor integrated circuits are connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition timing period corresponding to a delay time of said dummy device elements; said combination of semiconductor integrated circuits further including: a single counting means for said plurality of semiconductor integrated circuits connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal, a single delay time compensation control circuit for said plurality of semiconductor integrated circuits connected to said counting means for supplying control data based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation, a single synchronizing clock timing compensation circuit for said plurality of semiconductor integrated circuits connected to and receiving the control data from said delay time compensation control circuit for generating an output signal supplied to one of said logic circuits for compensating for a change in the signal propagation delay of said logic circuits, and a single oscillation delay control circuit for said plurality of semiconductor integrated circuits connected to and receiving the control data from said delay time compensation control circuit for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator.

Claim 6

A combination of semiconductor integrated circuits comprising: a plurality of semiconductor integrated circuits, each of said semiconductor integrated circuits comprising: a clock-synchronized logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements, and a plurality of dummy device elements connected in series, wherein said logic circuits of said plurality of semiconductor integrated circuits are connected in series and said plurality of dummy device elements of said plurality of semiconductor integrated circuits are connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition timing period corresponding to a delay time of said dummy device elements; said combination of semiconductor integrated circuits further including: a single counting means for said plurality of semiconductor integrated circuits connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal, a single delay time compensation control circuit for said plurality of semiconductor integrated circuits connected to said counting means for supplying control data based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation, a single synchronizing clock timing compensation circuit for said plurality of semiconductor integrated circuits connected to and receiving the control data from said delay time compensation control circuit for generating an output signal supplied to one of said logic circuits for compensating for a change in the signal propagation delay of said logic circuits, and a single oscillation delay control circuit for said plurality of semiconductor integrated circuits connected to and receiving the control data from said delay time compensation control circuit for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator.

Claim 7

A combination of semiconductor integrated circuits comprising: a plurality of semiconductor integrated circuits, each of said semiconductor integrated circuits comprising: a clock-synchronized logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements, a plurality of dummy device elements connected in series, and a power-supply voltage control circuit for controlling a power-supply voltage applied to said logic circuit and said plurality of dummy device elements, wherein said logic circuits of said plurality of semiconductor integrated circuits are connected in series and said plurality of dummy device elements of said plurality of semiconductor integrated circuits are connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition timing period corresponding to a delay time of said dummy device elements; said combination of semiconductor integrated circuits further including: a single counting means for said plurality of semiconductor integrated circuits connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal, and a single delay time compensation control circuit connected to said counting means for supplying a control voltage to said power-supply voltage control circuits of said plurality of semiconductor integrated circuits for compensating for a change in the signal propagation delay of said logic circuits, the control voltage being generated based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation.

Claim 8

A combination of semiconductor integrated circuits comprising: a plurality of semiconductor integrated circuits, each of said semiconductor integrated circuits comprising: a clock-synchronized logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements, a plurality of dummy device elements connected in series, and a power-supply voltage control circuit for controlling a power-supply voltage applied to said logic circuit and said plurality of dummy device elements, wherein said logic circuits of said plurality of semiconductor integrated circuits are connected in series and said plurality of dummy device elements of said plurality of semiconductor integrated circuits are connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition timing period corresponding to a delay time of said dummy device elements; said combination of semiconductor integrated circuits further including: a single counting means for said plurality of semiconductor integrated circuits connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal, and a single delay time compensation control circuit connected to said counting means for supplying a control voltage to said power-supply voltage control circuits of said plurality of semiconductor integrated circuits for compensating for a change in the signal propagation delay of said logic circuits, the control voltage being generated based on a difference between a count of said counting means and an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation.

Claim 9

A combination of semiconductor integrated circuits comprising: a plurality of channels, each of said channels comprising: a plurality of clock-synchronized integrated circuits including: logic circuits having respective signal propagation delays, each of said logic circuits for performing a predetermined logic operation and comprising a plurality of interconnected device elements, said logic circuits being connected in series, and a plurality of dummy device elements connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements, a single synchronizing clock timing compensation circuit for generating an output signal supplied to one of said logic circuits in each channel for compensating for a change in the signal propagation delay of said logic circuits, and a single oscillator delay control circuit for said plurality of integrated circuits for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator; wherein said combination of semiconductor integrated circuits further includes: a single counting means for said plurality of channels, said single counting means being connected for counting oscillating pulses generated by said ring oscillator of each channel relative to a reference pulse signal for each channel, a single memory means for said plurality of channels, said single memory means for storing compensation data for each of said plurality of channels, a single delay time compensation control circuit for said plurality of channels connected to said memory means and to said counting means for providing control data to said synchronizing clock timing compensation circuit and said oscillator delay control circuit for each channel, the control data being produced by retrieving compensation data from said memory means based on a count of said counting means, and selector means connected to said counting means, said delay time compensation control circuit, and said channels for selectively connecting respective channels to said counting means and said delay time compensation control circuit.

Claim 10

A combination of semiconductor integrated circuits comprising: a plurality of channels, each of said channels comprising: a plurality of clock-synchronized integrated circuits including: logic circuits having respective signal propagation delays, each of said logic circuits for performing a predetermined logic operation and comprising a plurality of interconnected device elements, said logic circuits being connected in series, and a plurality of dummy device elements connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements, a single synchronizing clock timing compensation circuit for generating an output signal supplied to one of said logic circuits in each channel for compensating for a change in the signal propagation delay of said logic circuits, and a single oscillator delay control circuit for said plurality of integrated circuits for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator; wherein said combination of semiconductor integrated circuits further includes: a single counting means for said plurality of channels, said single counting means being connected for counting oscillating pulses generated by said ring oscillator of each channel relative to a reference pulse signal for each channel, a single memory means for said plurality of channels, said single memory means for storing compensation data for each of said plurality of channels, a single delay time compensation control circuit for said plurality of channels connected to said memory means and to said counting means for providing control data to said synchronizing clock timing compensation circuit and said oscillator delay control circuit for each channel, the control data being produced by retrieving compensation data from said memory means based on a count of said counting means, and selector means connected to said counting means, said delay time compensation control circuit, and said channels for selectively connecting respective channels to said counting means and said delay time compensation control circuit.

Claim 11

A combination of semiconductor integrated circuits comprising: a plurality of channels, each of said plurality of channels comprising: a plurality of integrated circuits including: logic circuits having respective signal propagation delays, each of said logic circuits for performing a predetermined logic operation and comprising a plurality of interconnected device elements, said logic circuits being connected in series, a plurality of dummy device elements connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements, and a respective power-supply voltage control circuit for each of said logic circuits for controlling a power-supply voltage supplied to said logic circuits and corresponding dummy device elements; wherein said combination of semiconductor integrated circuits further includes: a single counting means for said plurality of channels, said single counting means being connected for counting oscillating pulses generated by said ring oscillator of each channel relative to a reference pulse signal for each channel, a single memory means for said plurality of channels for storing compensation data for each of said plurality of channels, a single delay time compensation control circuit for said plurality of channels connected to said memory means and to said counting means for generating compensation voltages provided to respective power-supply voltage control circuits of channels to compensate for a change in the propagation delay of said logic circuits, the compensation voltages being generated by retrieving compensation data from said memory means based on a count of said counting means, and transfer means connected to said counting means, said delay time compensation control circuit, and said channels for selectively transferring the compensation voltages generated by said delay time compensation control circuit to corresponding channels.

Claim 12

A combination of semiconductor integrated circuits comprising: a plurality of channels, each of said plurality of channels comprising: a plurality of integrated circuits including: logic circuits having respective signal propagation delays, each of said logic circuits for performing a predetermined logic operation and comprising a plurality of interconnected device elements, said logic circuits being connected in series, a plurality of dummy device elements connected in a ring to form a ring oscillator, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements, and a respective power-supply voltage control circuit for each of said logic circuits for controlling a power-supply voltage supplied to said logic circuits and corresponding dummy device elements; wherein said combination of semiconductor integrated circuits further includes: a single counting means for said plurality of channels, said single counting means being connected for counting oscillating pulses generated by said ring oscillator of each channel relative to a reference pulse signal for each channel, a single memory means for said plurality of channels for storing compensation data for each of said plurality of channels, a single delay time compensation control circuit for said plurality of channels connected to said memory means and to said counting means for generating compensation voltages provided to respective power-supply voltage control circuits of channels to compensate for a change in the propagation delay of said logic circuits, the compensation voltages being generated by retrieving compensation data from said memory means based on a count of said counting means, and transfer means connected to said counting means, said delay time compensation control circuit, and said channels for selectively transferring the compensation voltages generated by said delay time compensation control circuit to corresponding channels.

Claim 13

A semiconductor integrated circuit comprises: a logic circuit having a signal propagation delay, said logic circuit for perforating a predetermined logic operation comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; memory means for storing data indicating a stable state of stable oscillation of said ring oscillator, an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation, and status data representing states other than the stable state, said memory means storing, as compensation data, counts provided by said counting means in states other than the stable state; a delay time compensation control circuit connected to said memory means for generating a compensation voltage determined by retrieving compensation data from said memory means based on a difference between a count of said counting means and the initial count; and a power-supply voltage control circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for controlling a power supply voltage applied to said logic circuit and said ring oscillator to compensate for a change in the signal propagation delay of said logic circuit.

Claim 14

A semiconductor integrated circuit comprises: a logic circuit having a signal propagation delay, said logic circuit for perforating a predetermined logic operation comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; memory means for storing data indicating a stable state of stable oscillation of said ring oscillator, an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation, and status data representing states other than the stable state, said memory means storing, as compensation data, counts provided by said counting means in states other than the stable state; a delay time compensation control circuit connected to said memory means for generating a compensation voltage determined by retrieving compensation data from said memory means based on a difference between a count of said counting means and the initial count; and a power-supply voltage control circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for controlling a power supply voltage applied to said logic circuit and said ring oscillator to compensate for a change in the signal propagation delay of said logic circuit.

Claim 15

A semiconductor integrated circuit comprises: a logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; memory means for storing data indicating a stable state of stable oscillation of said ring oscillator, an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation, and status data representing states other than the stable state, said memory means storing, as compensation data, counts provided by said counting means in states other than the stable state; a delay time compensation control circuit connected to said counting means for generating a compensation voltage determined by retrieving compensation data from said memory means based on a difference between the count of said counting means and the initial count; a synchronizing clock timing compensation circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for generating an output signal supplied to said logic circuit for compensating for a change in the signal propagation delay of said logic circuit; and an oscillation delay control circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator.

Claim 16

A semiconductor integrated circuit comprises: a logic circuit having a signal propagation delay, said logic circuit for performing a predetermined logic operation and comprising a plurality of interconnected device elements; a ring oscillator comprising a plurality of dummy device elements, said dummy device elements being connected in a ring, an applied pulse being circulated through said dummy device elements to generate oscillating pulses with a repetition time period corresponding to a delay time of said dummy device elements; counting means connected to one of said dummy device elements for counting the oscillating pulses generated by said ring oscillator relative to a reference pulse signal; memory means for storing data indicating a stable state of stable oscillation of said ring oscillator, an initial count counted by said counting means when said integrated circuit first stabilizes after said ring oscillator begins oscillation, and status data representing states other than the stable state, said memory means storing, as compensation data, counts provided by said counting means in states other than the stable state; a delay time compensation control circuit connected to said counting means for generating a compensation voltage determined by retrieving compensation data from said memory means based on a difference between the count of said counting means and the initial count; a synchronizing clock timing compensation circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for generating an output signal supplied to said logic circuit for compensating for a change in the signal propagation delay of said logic circuit; and an oscillation delay control circuit connected to and receiving the compensation voltage from said delay time compensation control circuit for generating an output signal coupled to said ring oscillator for controlling the delay time of said ring oscillator.