US5073733A
Expired / Lapsed
US
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Delay circuit with muting to prevent noise due to random data at output
Assignee: Sanyo Electric Co Ltd
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Filing: 1990-04-18
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Granted: 1991-12-17
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Expires: 2010-04-18
Abstract
Abstract A delay circuit includes a memory addresses of which is designated by a counter incremented in response to each clock signal from an initial value set by an initial value setting circuit to an end value. A digital signal is written into an address as designated and read and converted into an analog signal to be outputted at an output terminal through a buffer amplifier. A delay time is determined by the writing timing and the reading timing of the digital signal. If the delay time is to be varied in the course of a delaying operation, a further initial value is set in the counter. A control signal for returning the counter in the initial value is generated by a first signal generating circuit when the end value is reached and a setting completion signal is generated by a second signal generating circuit when a setting of the further initial value is completed, and in response to both the signals, a muting signal is generated by a muting signal generating circuit, whereby the buffer amplifier mutes the output signal in response to the muting signal to prevent a noise due to random data from occurring at the output terminal.
Inventors
- 👤 Masaya Tanno
- 👤 Masato Onaya
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:40
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/135; H03K2005/00013; H03K2005/0015; H03K2005/00234; H03K2005/00247; H03K2005/0026; H03K2005/00267; H03K2005/00273
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
141 words
A delay circuit, comprising: an analog to digital (A/D) converting circuit for A/D converting an input signal; a memory for storing a digital signal outputted from said A/D converting circuit; a digital to analog (D/A) converting circuit for D/A converting a digital signal outputted from said memory; a counter for designating addresses to be used in said memory; an initial value setting circuit for initially setting an initial value of said counter; a first signal generating circuit for detecting that an end value of said counter is reached and for generating a control signal; a second signal generating circuit for generating a setting completion signal when an initial value setting operation by said initial value setting circuit is completed; and a muting signal generating circuit for generating a muting signal in response to said setting completion signal and said control signal.
Claim 2
Dependent Claim
141 words
A delay circuit, comprising: an analog to digital (A/D) converting circuit for A/D converting an input signal; a memory for storing a digital signal outputted from said A/D converting circuit; a digital to analog (D/A) converting circuit for D/A converting a digital signal outputted from said memory; a counter for designating addresses to be used in said memory; an initial value setting circuit for initially setting an initial value of said counter; a first signal generating circuit for detecting that an end value of said counter is reached and for generating a control signal; a second signal generating circuit for generating a setting completion signal when an initial value setting operation by said initial value setting circuit is completed; and a muting signal generating circuit for generating a muting signal in response to said setting completion signal and said control signal.
Claim 3
Dependent Claim
22 words
A delay circuit in accordance with claim 1, further comprising a muting circuit for muting an output of said D/A converting circuit.
Claim 4
Dependent Claim
46 words
A delay in accordance with claim 2, wherein said memory is constructed such that a plurality of addresses are sequentially designated in response to each address designating signal obtained from said counter, and a delay time is defined by the number of the addresses as designated.
Claim 5
Dependent Claim
103 words
A delay circuit in accordance with claim 3, wherein said muting signal generating circuit includes a first D-Flip Flop having a clock input to which said setting completion signal is applied, a second D-Flip Flop having a data input to which an output signal of said first D-Flip Flop is applied, a clock input to which said control signal is applied, and a gating circuit which generates a reset signal for said first D-Flip Flop in response to said control signal and an output of said second D-Flip Flop and to generate said muting signal at the output of said second D-Flip Flop.
Claim 6
Dependent Claim
122 words
A delay circuit, analog to digital (A/D) converting means for A/D converting an input signal; memory means for storing a digital signal outputted from said A/D converting means; digital to analog (D/A) converting means for D/A converting a digital outputted from said memory means; outputting means as a delayed signal; counter means for designating addresses to be used of said memory means; initial value setting means for initially setting an initial value of said counter means; signal generating means coupled to said counter means for generating a disabling signal; and disabling means for disabling substantially the output of said memory means to prevent a noise due to a random data read from said memory means from being outputted through said outputting means.
Claim 7
Dependent Claim
122 words
A delay circuit, analog to digital (A/D) converting means for A/D converting an input signal; memory means for storing a digital signal outputted from said A/D converting means; digital to analog (D/A) converting means for D/A converting a digital outputted from said memory means; outputting means as a delayed signal; counter means for designating addresses to be used of said memory means; initial value setting means for initially setting an initial value of said counter means; signal generating means coupled to said counter means for generating a disabling signal; and disabling means for disabling substantially the output of said memory means to prevent a noise due to a random data read from said memory means from being outputted through said outputting means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-16 | 1995-06-17 | 1995-12-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-16 | 1999-06-17 | 1999-12-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-16 | 2003-06-17 | 2003-12-17 | $7700.00 | Window Closed / Lapsed |