Apparatus for controlling a signal processing system to operate in high and low speed modes

Claim 1

An apparatus for controlling a digital signal processing system including a plurality of peripheral devices to operate in high and low speed modes comprising: a memory in which a predetermined program is stored, said program including a plurality of instructions, and a central processing unit (CPU) including a clock input terminal for receiving an externally applied clock signal, a circuit for selectively producing system clock signals defining said high and low speed modes by selective frequency division of said externally applied clock signal by first and second divisors in response to a change speed instruction and supplying said system clock signals to said plurality of peripheral devices via a common clock output terminal, and control means for controlling said circuit to produce said system clock signals for said high and low speed modes in response to instructions of said program, wherein said control means selectively produces a mode signal corresponding to one mode selected from said high and low speed modes and supplies the selected mode signal to said plurality of peripheral devices during continuous processing operation without processing initialization, the digital signal processing changes from the low speed mode to the high speed mode after one bus cycle passes in accordance with said change speed instruction, and a non-operation command is provided between a change speed high command and a change speed low command.

Claim 2

An apparatus for controlling a digital signal processing system including a plurality of peripheral devices to operate in high and low speed modes comprising: a memory in which a predetermined program is stored, said program including a plurality of instructions, and a central processing unit (CPU) including a clock input terminal for receiving an externally applied clock signal, a circuit for selectively producing system clock signals defining said high and low speed modes by selective frequency division of said externally applied clock signal by first and second divisors in response to a change speed instruction and supplying said system clock signals to said plurality of peripheral devices via a common clock output terminal, and control means for controlling said circuit to produce said system clock signals for said high and low speed modes in response to instructions of said program, wherein said control means selectively produces a mode signal corresponding to one mode selected from said high and low speed modes and supplies the selected mode signal to said plurality of peripheral devices during continuous processing operation without processing initialization, the digital signal processing changes from the low speed mode to the high speed mode after one bus cycle passes in accordance with said change speed instruction, and a non-operation command is provided between a change speed high command and a change speed low command.

Claim 4

An apparatus for generating a video signal to be displayed on a video monitor in response to a program, comprising: memory means for storing the program; central processing unit (CPU) including a clock input terminal for receiving an externally applied clock signal, and scaling means responsive to said externally applied clock signal and to a change speed command for selectively supplying first and second internal clock signals to a peripheral circuit via a common clock output terminal, each of said first and second clock signals having a frequency which is a different sub-multiple of the frequency of said externally applied clock signal during continuous processing without processing initialization, digital processing means responsive to the internally supplied clock signals for accessing said program memory and, in response, supplying a video output signal and a control signal; and terminal means for supplying said control signal to said peripheral circuit external to said apparatus, wherein the apparatus changes from a low speed mode to a high speed mode after one bus cycle passes in accordance with said change speed command, and a non-operation command is provided between a change speed high command and a change speed low command.

Claim 5

An apparatus for generating a video signal to be displayed on a video monitor in response to a program, comprising: memory means for storing the program; central processing unit (CPU) including a clock input terminal for receiving an externally applied clock signal, and scaling means responsive to said externally applied clock signal and to a change speed command for selectively supplying first and second internal clock signals to a peripheral circuit via a common clock output terminal, each of said first and second clock signals having a frequency which is a different sub-multiple of the frequency of said externally applied clock signal during continuous processing without processing initialization, digital processing means responsive to the internally supplied clock signals for accessing said program memory and, in response, supplying a video output signal and a control signal; and terminal means for supplying said control signal to said peripheral circuit external to said apparatus, wherein the apparatus changes from a low speed mode to a high speed mode after one bus cycle passes in accordance with said change speed command, and a non-operation command is provided between a change speed high command and a change speed low command.

Claim 8

An apparatus for controlling a signal processing system to operate in high and low speed modes, comprising: a memory for storing a program including a high speed operation command and a low speed operation command; a central processing unit (CPU) including a clock input terminal for receiving an externally applied clock signal, and a circuit for selectively producing first and second system clock signals defining said high and low speed modes by selective frequency division of said externally applied clock signal by first and second divisors, and supplying the selectively produced said first and second system clock signals to a peripheral circuit via a common clock output terminal; and means for controlling said circuit for selectively producing first and second system clock signals to produce said first and second system clock signals for said high and low speed modes in response to said high and low speed operation commands; wherein said means for controlling selectively produces a mode signal corresponding to one mode selected from said high and low speed modes and supplies a selected mode signal to said peripheral circuit together with the selectively produced said first and second system clock signals, and controls said peripheral circuit to operate in said selected mode, one of said high and low speed operation commands being conducted in one bus cycle equal to one period of said system clock signal for said selected mode, so that change-over between said high and low speed modes in carried out without initialization of said signal processing system, the signal processing system changes from the low speed mode to the high speed mode after one bus cycle passes in accordance with the high speed operation command, and a non-operation command is provided between a change speed high command and a change speed low command.

Claim 9

An apparatus for controlling a signal processing system to operate in high and low speed modes, comprising: a memory for storing a program including a high speed operation command and a low speed operation command; a central processing unit (CPU) including a clock input terminal for receiving an externally applied clock signal, and a circuit for selectively producing first and second system clock signals defining said high and low speed modes by selective frequency division of said externally applied clock signal by first and second divisors, and supplying the selectively produced said first and second system clock signals to a peripheral circuit via a common clock output terminal; and means for controlling said circuit for selectively producing first and second system clock signals to produce said first and second system clock signals for said high and low speed modes in response to said high and low speed operation commands; wherein said means for controlling selectively produces a mode signal corresponding to one mode selected from said high and low speed modes and supplies a selected mode signal to said peripheral circuit together with the selectively produced said first and second system clock signals, and controls said peripheral circuit to operate in said selected mode, one of said high and low speed operation commands being conducted in one bus cycle equal to one period of said system clock signal for said selected mode, so that change-over between said high and low speed modes in carried out without initialization of said signal processing system, the signal processing system changes from the low speed mode to the high speed mode after one bus cycle passes in accordance with the high speed operation command, and a non-operation command is provided between a change speed high command and a change speed low command.