Microcomputer having a high-speed operation mode and a low-speed operation mode with intermittent disabling of sense amplifiers

Claim 1

A microcomputer comprising a memory having a plurality of bit lines and a dummy line, a first current mirror type sense amplifier having a current input terminal connected to one of said plurality of bit lines through a first switching circuit, a second current mirror type sense amplifier having a current input terminal connected to said dummy line through a second switching circuit, a signal derived from an output terminal of said second current mirror type sense amplifier being applied as a reference signal to said first current mirror type sense amplifier, an output of said memory being derived from an output terminal of said first current mirror type sense amplifier, a first means for selectively generating a first enable signal which is always activated in a high-speed operation mode and a second enable signal which is intermittently activated in a low-speed operation mode, and a second means coupled between said first means and said first and second switching circuits for controlling said first and second switching circuits according to said first and second enable signals in such manner that said first and second switching circuits are continuously turned on in response to the activated state of said first enable signal thereby to continuously enable said first and second current mirror type sense amplifiers, and are intermittently turned on in response to the activate state of said second enable signal thereby to intermittently enable said first and second current mirror type sense amplifiers.